commit 32dbaafa5a1fda97dbf99e6627309e7570dc14ca
author Alison Wang <b18965@freescale.com> Mon Mar 26 21:49:04 2012 +0000
committer jason <jason@jason-ThinkPad-T61.(none)> Thu Sep 20 20:39:26 2012 +0800
tree 9ebd26f798f8b24dcd6c8af1967605daec0246eb
parent 849fc424713d176f90af0b05f6161bc3803ca887

ColdFire: Clean up checkpatch warnings for MCF52x2

Signed-off-by: Alison Wang <b18965@freescale.com>

arch/m68k/cpu/mcf52x2/interrupts.c

diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index dff8c6a..915eb70 100644
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,20 +28,22 @@
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #ifdef	CONFIG_M5272
 int interrupt_init(void)
 {
-	volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
+	intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
 
 	/* disable all external interrupts */
-	intp->int_icr1 = 0x88888888;
-	intp->int_icr2 = 0x88888888;
-	intp->int_icr3 = 0x88888888;
-	intp->int_icr4 = 0x88888888;
-	intp->int_pitr = 0x00000000;
+	out_be32(&intp->int_icr1, 0x88888888);
+	out_be32(&intp->int_icr2, 0x88888888);
+	out_be32(&intp->int_icr3, 0x88888888);
+	out_be32(&intp->int_icr4, 0x88888888);
+	out_be32(&intp->int_pitr, 0x00000000);
+
 	/* initialize vector register */
-	intp->int_pivr = 0x40;
+	out_8(&intp->int_pivr, 0x40);
 
 	enable_interrupts();
 
@@ -51,10 +53,10 @@
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+	intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
-	intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
+	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
+	setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
@@ -63,14 +65,14 @@
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 #if defined(CONFIG_M5208)
-	intp->imrl0 = 0xFFFFFFFF;
-	intp->imrh0 = 0xFFFFFFFF;
+	out_be32(&intp->imrl0, 0xffffffff);
+	out_be32(&intp->imrh0, 0xffffffff);
 #else
-	intp->imrl0 |= 0x1;
+	setbits_be32(&intp->imrl0, 0x1);
 #endif
 
 	enable_interrupts();
@@ -80,11 +82,11 @@
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrl0 &= 0xFFFFFFFE;
-	intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrl0, 0x00000001);
+	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */