commit 32dbaafa5a1fda97dbf99e6627309e7570dc14ca
author Alison Wang <b18965@freescale.com> Mon Mar 26 21:49:04 2012 +0000
committer jason <jason@jason-ThinkPad-T61.(none)> Thu Sep 20 20:39:26 2012 +0800
tree 9ebd26f798f8b24dcd6c8af1967605daec0246eb
parent 849fc424713d176f90af0b05f6161bc3803ca887

ColdFire: Clean up checkpatch warnings for MCF52x2

Signed-off-by: Alison Wang <b18965@freescale.com>

board/freescale/m5253demo/m5253demo.c

diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 8ffb2cc..052993d 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -109,7 +109,7 @@
 
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
@@ -120,7 +120,8 @@
 	};
 
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(100);
 	} else {
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
@@ -129,17 +130,19 @@
 		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
-		ata->t2w = CALC_TIMING(piotms[2][1]);
-		ata->t2r = CALC_TIMING(piotms[2][1]);
-		ata->ta = CALC_TIMING(piotms[2][8]);
-		ata->trd = CALC_TIMING(piotms[2][7]);
-		ata->t4 = CALC_TIMING(piotms[2][3]);
-		ata->t9 = CALC_TIMING(piotms[2][6]);
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
 
-		ata->cr = 0x40;	/* IORDY enable */
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(2000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif				/* CONFIG_CMD_IDE */