ARM: socfpga: Repair A10 EMAC reset handling
The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index f909568..e1d80a5 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -41,8 +41,7 @@
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
-void dwmac_deassert_reset(const unsigned int of_reset_id,
- const u32 phymode)
+static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode)
{
u32 reset;
@@ -64,6 +63,20 @@
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
}
+
+static int socfpga_eth_reset(void)
+{
+ /* Put all GMACs into RESET state. */
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1);
+ return socfpga_eth_reset_common(arria10_dwmac_reset);
+};
+#else
+static int socfpga_eth_reset(void)
+{
+ return 0;
+};
#endif
#if defined(CONFIG_SPL_BUILD)
@@ -251,6 +264,6 @@
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
- return 0;
+ return socfpga_eth_reset();
}
#endif