| commit | 334e442e6fac59be91244063e9b3f6ca25e8daf8 | [log] [tgz] |
|---|---|---|
| author | Grzegorz Bernacki <gjb@semihalf.com> | Wed Jan 16 15:12:47 2008 +0100 |
| committer | Wolfgang Denk <wd@denx.de> | Thu Jan 17 09:31:58 2008 +0100 |
| tree | 8e3ba14866674209e364e7617efc647da1d21168 | |
| parent | 4c9e98ace78e7de972adf7da7135a46ec0a4ee7e [diff] |
Set ips dividor to 1/4 of csb clock. Previous setting cause ips clock to be out of spec. This bug was found by John Rigby from Freescale. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>