clk: sunxi: Add Allwinner H6 CLK driver
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index a6f84e9..cb11c7c 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -65,6 +65,13 @@
This enables common clock driver support for platforms based
on Allwinner H3/H5 SoC.
+config CLK_SUN50I_H6
+ bool "Clock driver for Allwinner H6"
+ default MACH_SUN50I_H6
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner H6 SoC.
+
config CLK_SUN50I_A64
bool "Clock driver for Allwinner A64"
default MACH_SUN50I