usb: dwc2: Rename CONFIG_DWC2 namespace to DWC2
There are a number of DWC2 configuration options that are set in dwc2.h
and referenced in dwc2.c only. Move these out of the CONFIG_DWC2
namespace and in to the DWC2 namespace. Note that hikey was defining an
option that was already always enabled, so we can remove that hunk.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 43cc2e0..23060fc 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -86,14 +86,14 @@
{
uint32_t phyclk;
-#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
#else
/* High speed PHY running at full speed or high speed */
phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
#endif
-#ifdef CONFIG_DWC2_ULPI_FS_LS
+#ifdef DWC2_ULPI_FS_LS
uint32_t hwcfg2 = readl(®s->ghwcfg2);
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
@@ -257,28 +257,28 @@
/* Initialize Host Configuration Register */
init_fslspclksel(regs);
-#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
+#ifdef DWC2_DFLT_SPEED_FULL
setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
#endif
/* Configure data FIFO sizes */
-#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+#ifdef DWC2_ENABLE_DYNAMIC_FIFO
if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
/* Rx FIFO */
- writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
+ writel(DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
/* Non-periodic Tx FIFO */
- nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
+ nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
DWC2_FIFOSIZE_DEPTH_OFFSET;
- nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
+ nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE <<
DWC2_FIFOSIZE_STARTADDR_OFFSET;
writel(nptxfifosize, ®s->gnptxfsiz);
/* Periodic Tx FIFO */
- ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
+ ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE <<
DWC2_FIFOSIZE_DEPTH_OFFSET;
- ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
- CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
+ ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE +
+ DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
DWC2_FIFOSIZE_STARTADDR_OFFSET;
writel(ptxfifosize, ®s->hptxfsiz);
}
@@ -340,7 +340,7 @@
struct dwc2_core_regs *regs = priv->regs;
uint32_t ahbcfg = 0;
uint32_t usbcfg = 0;
- uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
+ uint8_t brst_sz = DWC2_DMA_BURST_SIZE;
/* Common Initialization */
usbcfg = readl(®s->gusbcfg);
@@ -357,7 +357,7 @@
}
/* Set external TS Dline pulsing */
-#ifdef CONFIG_DWC2_TS_DLINE
+#ifdef DWC2_TS_DLINE
usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
#else
usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
@@ -371,8 +371,8 @@
* This programming sequence needs to happen in FS mode before
* any other programming occurs
*/
-#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
- (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+#if defined(DWC2_DFLT_SPEED_FULL) && \
+ (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
/* If FS mode with FS PHY */
setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
@@ -387,7 +387,7 @@
if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
init_fslspclksel(regs);
-#ifdef CONFIG_DWC2_I2C_ENABLE
+#ifdef DWC2_I2C_ENABLE
/* Program GUSBCFG.OtgUtmifsSel to I2C */
setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
@@ -407,16 +407,16 @@
* immediately after setting phyif.
*/
usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
- usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
+ usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
-#ifdef CONFIG_DWC2_PHY_ULPI_DDR
+#ifdef DWC2_PHY_ULPI_DDR
usbcfg |= DWC2_GUSBCFG_DDRSEL;
#else
usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
#endif
} else { /* UTMI+ interface */
-#if (CONFIG_DWC2_UTMI_WIDTH == 16)
+#if (DWC2_UTMI_WIDTH == 16)
usbcfg |= DWC2_GUSBCFG_PHYIF;
#endif
}
@@ -429,7 +429,7 @@
usbcfg = readl(®s->gusbcfg);
usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
-#ifdef CONFIG_DWC2_ULPI_FS_LS
+#ifdef DWC2_ULPI_FS_LS
uint32_t hwcfg2 = readl(®s->ghwcfg2);
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
@@ -456,14 +456,14 @@
brst_sz >>= 1;
}
-#ifdef CONFIG_DWC2_DMA_ENABLE
+#ifdef DWC2_DMA_ENABLE
ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
#endif
break;
case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
-#ifdef CONFIG_DWC2_DMA_ENABLE
+#ifdef DWC2_DMA_ENABLE
ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
#endif
break;
@@ -476,7 +476,7 @@
if (!priv->hnp_srp_disable)
usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
-#ifdef CONFIG_DWC2_IC_USB_CAP
+#ifdef DWC2_IC_USB_CAP
usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
#endif
@@ -939,9 +939,9 @@
debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
in, len);
- max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
- if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
- max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
+ max_xfer_len = DWC2_MAX_PACKET_COUNT * max;
+ if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE)
+ max_xfer_len = DWC2_MAX_TRANSFER_SIZE;
if (max_xfer_len > DWC2_DATA_BUF_SIZE)
max_xfer_len = DWC2_DATA_BUF_SIZE;
@@ -1198,7 +1198,7 @@
return -ENODEV;
}
-#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+#ifdef DWC2_PHY_ULPI_EXT_VBUS
priv->ext_vbus = 1;
#else
priv->ext_vbus = 0;