phy: marvell: add support for SFI1
In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.
In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0
No functional change for exsiting configuration.
Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index f475fb3..b158f92 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -132,7 +132,8 @@
};
phy2 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy3 {
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index ce5832c..6a586db 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -154,7 +154,7 @@
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: Not connected
- * Lane 2: SFI (10G)
+ * Lane 2: SFI0 (10G)
* Lane 3: Not connected
* Lane 4: USB 3.0 host port1 (can be PCIe)
* Lane 5: Not connected
@@ -166,7 +166,7 @@
phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_UNCONNECTED>;
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 1edfaab..51c2f23 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -95,7 +95,7 @@
phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_SATA1>;
@@ -194,7 +194,7 @@
phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_SATA1>;
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index a6ef401..2184648 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -183,7 +183,7 @@
phy-type = <COMPHY_TYPE_PEX0>;
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
@@ -299,7 +299,7 @@
phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SGMII2>;
diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts
index 0becc4f..510fb84 100644
--- a/arch/arm/dts/armada-8040-puzzle-m801.dts
+++ b/arch/arm/dts/armada-8040-puzzle-m801.dts
@@ -234,7 +234,7 @@
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
@@ -380,7 +380,7 @@
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SGMII2>;
diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts
index 5c5e0fb..fcfcd15 100644
--- a/arch/arm/dts/cn9130-crb-A.dts
+++ b/arch/arm/dts/cn9130-crb-A.dts
@@ -31,7 +31,7 @@
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};
diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts
index 6041084..b681b60 100644
--- a/arch/arm/dts/cn9130-crb-B.dts
+++ b/arch/arm/dts/cn9130-crb-B.dts
@@ -31,7 +31,7 @@
};
phy4 {
- phy-type = <COMPHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};