ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure
and nobody seems to have time / resources to port this over to the newer
SPL infrastructure, lets remove NAND booting completely.
This should not affect the "normal", non NAND-booting ppc4xx platforms
that are currently supported.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tirumala Marri <tmarri@apm.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 61bfea3..9673118 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -17,7 +17,6 @@
extern void board_pll_init_f(void);
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
static void cram_bcr_write(u32 wr_val)
{
wr_val <<= 2;
@@ -41,20 +40,9 @@
return;
}
-#endif
phys_size_t initdram(int board_type)
{
-#if defined(CONFIG_NAND_SPL)
- u32 reg;
-
- /* don't reinit PLL when booting via I2C bootstrap option */
- mfsdr(SDR0_PINSTP, reg);
- if (reg != 0xf0000000)
- board_pll_init_f();
-#endif
-
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
int i;
u32 val;
@@ -88,7 +76,6 @@
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
;
-#endif
return (CONFIG_SYS_MBYTES_RAM << 20);
}
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c
index d74b725..d868582 100644
--- a/board/amcc/acadia/pll.c
+++ b/board/amcc/acadia/pll.c
@@ -135,45 +135,3 @@
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
-
-#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
-/*
- * Get timebase clock frequency
- */
-unsigned long get_tbclk(void)
-{
- unsigned long cpr_plld;
- unsigned long cpr_primad;
- unsigned long primad_cpudv;
- unsigned long pllFbkDiv;
- unsigned long freqProcessor;
-
- /*
- * Read PLL Mode registers
- */
- mfcpr(CPR0_PLLD, cpr_plld);
-
- /*
- * Read CPR_PRIMAD register
- */
- mfcpr(CPR0_PRIMAD, cpr_primad);
-
- /*
- * Determine CPU clock frequency
- */
- primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
- if (primad_cpudv == 0)
- primad_cpudv = 16;
-
- /*
- * Determine FBK_DIV.
- */
- pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
- if (pllFbkDiv == 0)
- pllFbkDiv = 256;
-
- freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
-
- return (freqProcessor);
-}
-#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 84bbacf..c8d0963 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -16,7 +16,6 @@
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
/*************************************************************************
*
* Bamboo has one bank onboard sdram (plus DIMM)
@@ -178,7 +177,6 @@
0,
0
};
-#endif
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
@@ -440,15 +438,11 @@
phys_size_t initdram (int board_type)
{
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;
dram_size = spd_sdram();
return dram_size;
-#else
- return CONFIG_SYS_MBYTES_SDRAM << 20;
-#endif
}
/*----------------------------------------------------------------------------+
@@ -1794,23 +1788,12 @@
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
{
update_ndfc_ios(gpio_tab);
-
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
-#else
- mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
- SDR0_CUST0_NDFC_ENABLE |
- SDR0_CUST0_NDFC_BW_8_BIT |
- SDR0_CUST0_NDFC_ARE_MASK |
- SDR0_CUST0_CHIPSELGAT_EN0 |
- SDR0_CUST0_CHIPSELGAT_EN2);
-#endif
-
ndfc_selection_in_fpga();
}
else
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 48dbcbe..5c7c839 100644
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -32,12 +32,7 @@
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
-#else
- tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
-#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
@@ -58,31 +53,3 @@
tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 2b5f1a6..79d4bab 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -379,11 +379,7 @@
*/
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
- mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-#else
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-#endif
/* Remove TLB entry of boot EBC mapping */
remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index d83cd6e..bf00bd6 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -31,13 +31,7 @@
* use the speed up boot process. It is patched after relocation to
* enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
-#else
- tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
- tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
-#endif
/*
* TLB entries for SDRAM are not needed on this platform.
@@ -95,31 +89,3 @@
#endif
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,0x0000 /* TLB entry #0 */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index b31e9db..f876639 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -48,11 +48,7 @@
/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
-#ifndef CONFIG_NAND_SPL
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-#else
- tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
-#endif
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
@@ -81,31 +77,3 @@
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * For NAND booting the first TLB has to be reconfigured to full size
- * and with caching disabled after running from RAM!
- */
-#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_RWX | SA_IG)
-
- .globl reconfig_tlb0
-reconfig_tlb0:
- sync
- isync
- addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
- lis r5,TLB00@h
- ori r5,r5,TLB00@l
- tlbwe r5,r4,0x0000 /* Save it out */
- lis r5,TLB01@h
- ori r5,r5,TLB01@l
- tlbwe r5,r4,0x0001 /* Save it out */
- lis r5,TLB02@h
- ori r5,r5,TLB02@l
- tlbwe r5,r4,0x0002 /* Save it out */
- sync
- isync
- blr
-#endif
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 2c5a218..67640d7 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -26,14 +26,6 @@
extern int denali_wait_for_dlllock(void);
extern void denali_core_search_data_eye(void);
-#if defined(CONFIG_NAND_SPL)
-/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
- * for the 4k NAND boot image so define bus_frequency to 133MHz here
- * which is save for the refresh counter setup.
- */
-#define get_bus_freq(val) 133333333
-#endif
-
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@@ -41,8 +33,7 @@
************************************************************************/
phys_size_t initdram (int board_type)
{
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
- defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_SYS_RAMBOOT)
ulong speed = get_bus_freq(0);
mtsdram(DDR0_02, 0x00000000);
@@ -81,7 +72,7 @@
mtsdram(DDR0_02, 0x00000001);
denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+#endif /* #ifndef CONFIG_SYS_RAMBOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 73c65c5..53f9b34 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -142,8 +142,7 @@
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
- defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
@@ -151,8 +150,7 @@
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
- defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
@@ -360,7 +358,7 @@
}
#endif
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
/*
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
@@ -411,4 +409,4 @@
return;
}
}
-#endif /* CONFIG_NAND_U_BOOT */
+#endif /* CONFIG_SYS_RAMBOOT */