Merge tag 'efi-2021-04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2021-04-rc1
In the UEFI sub-system:
* implement non-blocking file services
* print boot device and file path in helloworld.efi
* improve detection of boot device
* correct argument handling in efivar.py
* implement EFI_DT_FIXUP_PROTOCOL
Bug fixes:
* adjust conitrace command for low baud rates
* check that FIT images are valid FDTs
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0f738c2..a9d36e0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -161,14 +161,19 @@
meson-gxl-s905x-p212.dtb \
meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905x-libretech-cc.dtb \
+ meson-gxl-s905x-libretech-cc-v2.dtb \
meson-gxl-s905x-khadas-vim.dtb \
meson-gxl-s905d-libretech-pc.dtb \
meson-gxm-khadas-vim2.dtb \
meson-gxm-s912-libretech-pc.dtb \
+ meson-gxm-wetek-core2.dtb \
meson-axg-s400.dtb \
meson-g12a-u200.dtb \
meson-g12a-sei510.dtb \
+ meson-g12b-gtking.dtb \
+ meson-g12b-gtking-pro.dtb \
meson-g12b-odroid-n2.dtb \
+ meson-g12b-odroid-n2-plus.dtb \
meson-g12b-a311d-khadas-vim3.dtb \
meson-sm1-khadas-vim3l.dtb \
meson-sm1-odroid-c4.dtb \
diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi
index 8e6281c..b9efc84 100644
--- a/arch/arm/dts/meson-axg.dtsi
+++ b/arch/arm/dts/meson-axg.dtsi
@@ -181,8 +181,10 @@
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1",
+ "timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
status = "disabled";
diff --git a/arch/arm/dts/meson-g12b-gtking-pro.dts b/arch/arm/dts/meson-g12b-gtking-pro.dts
new file mode 100644
index 0000000..f0c56a1
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-gtking-pro.dts
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-w400.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "azw,gtking", "amlogic,g12b";
+ model = "Beelink GT-King Pro";
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <100>;
+
+ power-button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ white {
+ label = "power:white";
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "G12B-GTKING-PRO";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
diff --git a/arch/arm/dts/meson-g12b-gtking.dts b/arch/arm/dts/meson-g12b-gtking.dts
new file mode 100644
index 0000000..eeb7bc5
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-gtking.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-w400.dtsi"
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "azw,gtking", "amlogic,g12b";
+ model = "Beelink GT-King";
+
+ spdif_dit: audio-codec-1 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "G12B-GTKING";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "SPDIFOUT IN 0", "FRDDR_A OUT 3",
+ "SPDIFOUT IN 1", "FRDDR_B OUT 3",
+ "SPDIFOUT IN 2", "FRDDR_C OUT 3";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* spdif hdmi or toslink interface */
+ dai-link-4 {
+ sound-dai = <&spdifout>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+
+ codec-1 {
+ sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
+ };
+ };
+
+ /* spdif hdmi interface */
+ dai-link-5 {
+ sound-dai = <&spdifout_b>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-6 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&spdifout {
+ pinctrl-0 = <&spdif_out_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spdifout_b {
+ status = "okay";
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
diff --git a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi b/arch/arm/dts/meson-g12b-khadas-vim3.dtsi
index 224c890..f42cf4b 100644
--- a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi
+++ b/arch/arm/dts/meson-g12b-khadas-vim3.dtsi
@@ -5,8 +5,6 @@
* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
*/
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
/ {
model = "Khadas VIM3";
@@ -47,69 +45,6 @@
regulator-boot-on;
regulator-always-on;
};
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "G12B-KHADAS-VIM3";
- audio-aux-devs = <&tdmout_a>;
- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
- "TDMOUT_A IN 1", "FRDDR_B OUT 0",
- "TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_a>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
};
&cpu0 {
@@ -154,18 +89,6 @@
clock-latency = <50000>;
};
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
&pwm_ab {
pinctrl-0 = <&pwm_a_e_pins>;
pinctrl-names = "default";
@@ -182,14 +105,3 @@
status = "okay";
};
-&tdmif_a {
- status = "okay";
-};
-
-&tdmout_a {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts b/arch/arm/dts/meson-g12b-odroid-n2-plus.dts
new file mode 100644
index 0000000..5de2815
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-odroid-n2-plus.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */
+#include "meson-g12b-a311d.dtsi"
+#include "meson-g12b-odroid-n2.dtsi"
+
+/ {
+ compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b";
+ model = "Hardkernel ODROID-N2Plus";
+};
+
+&vddcpu_a {
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwms = <&pwm_AO_cd 1 1500 0>;
+};
+
+&vddcpu_b {
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwms = <&pwm_AO_cd 1 1500 0>;
+};
+
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
index 34fffa6..a198a91 100644
--- a/arch/arm/dts/meson-g12b-odroid-n2.dts
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dts
@@ -7,625 +7,9 @@
/dts-v1/;
#include "meson-g12b-s922x.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-toacodec.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+#include "meson-g12b-odroid-n2.dtsi"
/ {
compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b";
model = "Hardkernel ODROID-N2";
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- dioo2133: audio-amplifier-0 {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
- VCC-supply = <&vcc_5v>;
- sound-name-prefix = "U19";
- status = "okay";
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- blue {
- label = "n2:blue";
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
-
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- tf_io: gpio-regulator-tf_io {
- compatible = "regulator-gpio";
-
- regulator-name = "TF_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
- };
-
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- vin-supply = <&main_12v>;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddcpu_a: regulator-vddcpu-a {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_A";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_ab 0 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddcpu_b: regulator-vddcpu-b {
- /*
- * Silergy SY8120B1ABC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_B";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- hub_5v: regulator-hub_5v {
- compatible = "regulator-fixed";
- regulator-name = "HUB_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the Hub CHIPENABLE, LOW sets low power state */
- gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the microUSB port power enable */
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "G12B-ODROID-N2";
- audio-widgets = "Line", "Lineout";
- audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
- <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
- <&dioo2133>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT",
- "TDMOUT_C IN 0", "FRDDR_A OUT 2",
- "TDMOUT_C IN 1", "FRDDR_B OUT 2",
- "TDMOUT_C IN 2", "FRDDR_C OUT 2",
- "TDM_C Playback", "TDMOUT_C OUT",
- "TDMIN_A IN 4", "TDM_B Loopback",
- "TDMIN_B IN 4", "TDM_B Loopback",
- "TDMIN_C IN 4", "TDM_B Loopback",
- "TDMIN_LB IN 1", "TDM_B Loopback",
- "TDMIN_A IN 5", "TDM_C Loopback",
- "TDMIN_B IN 5", "TDM_C Loopback",
- "TDMIN_C IN 5", "TDM_C Loopback",
- "TDMIN_LB IN 2", "TDM_C Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT",
- "TODDR_A IN 1", "TDMIN_B OUT",
- "TODDR_B IN 1", "TDMIN_B OUT",
- "TODDR_C IN 1", "TDMIN_B OUT",
- "TODDR_A IN 2", "TDMIN_C OUT",
- "TODDR_B IN 2", "TDMIN_C OUT",
- "TODDR_C IN 2", "TDMIN_C OUT",
- "TODDR_A IN 6", "TDMIN_LB OUT",
- "TODDR_B IN 6", "TDMIN_LB OUT",
- "TODDR_C IN 6", "TDMIN_LB OUT",
- "U19 INL", "ACODEC LOLP",
- "U19 INR", "ACODEC LORP",
- "Lineout", "U19 OUTL",
- "Lineout", "U19 OUTR";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- dai-link-3 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-4 {
- sound-dai = <&toddr_b>;
- };
-
- dai-link-5 {
- sound-dai = <&toddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-6 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
-
- codec-1 {
- sound-dai = <&toacodec TOACODEC_IN_B>;
- };
- };
-
- /* i2s jack output interface */
- dai-link-7 {
- sound-dai = <&tdmif_c>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
- };
-
- codec-1 {
- sound-dai = <&toacodec TOACODEC_IN_C>;
- };
- };
-
- /* hdmi glue */
- dai-link-8 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
-
- /* acodec glue */
- dai-link-9 {
- sound-dai = <&toacodec TOACODEC_OUT>;
-
- codec {
- sound-dai = <&acodec>;
- };
- };
- };
-};
-
-&acodec {
- AVDD-supply = <&vddao_1v8>;
- status = "okay";
-};
-
-&arb {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
- reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&gpio {
- /*
- * WARNING: The USB Hub on the Odroid-N2 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- usb-hub {
- gpio-hog;
- gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
- linux,rc-map-name = "rc-odroid";
-};
-
-&pwm_ab {
- pinctrl-0 = <&pwm_a_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&tf_io>;
-
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
-
-/*
- * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
- * and eMMC Data 4 to 7 pins.
- * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
- * and change bus-width to 4 then spifc can be enabled.
- * The SW1 slide should also be set to the correct position.
- */
-&spifc {
- status = "disabled";
- pinctrl-0 = <&nor_pins>;
- pinctrl-names = "default";
-
- mx25u64: spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <104000000>;
- };
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmif_c {
- status = "okay";
-};
-
-&tdmin_a {
- status = "okay";
-};
-
-&tdmin_b {
- status = "okay";
-};
-
-&tdmin_c {
- status = "okay";
-};
-
-&tdmin_lb {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tdmout_c {
- status = "okay";
-};
-
-&toacodec {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&toddr_b {
- status = "okay";
-};
-
-&toddr_c {
- status = "okay";
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- vbus-supply = <&usb_pwr_en>;
-};
-
-&usb2_phy0 {
- phy-supply = <&vcc_5v>;
-};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&hub_5v>;
};
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
new file mode 100644
index 0000000..6982632
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
@@ -0,0 +1,625 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ dioo2133: audio-amplifier-0 {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ VCC-supply = <&vcc_5v>;
+ sound-name-prefix = "U19";
+ status = "okay";
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ label = "n2:blue";
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ tf_io: gpio-regulator-tf_io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ main_12v: regulator-main_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ vin-supply = <&main_12v>;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ /*
+ * MP8756GD Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&main_12v>;
+
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ /*
+ * Silergy SY8120B1ABC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&main_12v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ hub_5v: regulator-hub_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "HUB_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the Hub CHIPENABLE, LOW sets low power state */
+ gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_pwr_en: regulator-usb_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to the microUSB port power enable */
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_12v>;
+ regulator-always-on;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "G12B-ODROID-N2";
+ audio-widgets = "Line", "Lineout";
+ audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
+ <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
+ <&dioo2133>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TDMIN_C IN 4", "TDM_B Loopback",
+ "TDMIN_LB IN 1", "TDM_B Loopback",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TDMIN_LB IN 2", "TDM_C Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "TODDR_A IN 6", "TDMIN_LB OUT",
+ "TODDR_B IN 6", "TDMIN_LB OUT",
+ "TODDR_C IN 6", "TDMIN_LB OUT",
+ "U19 INL", "ACODEC LOLP",
+ "U19 INR", "ACODEC LORP",
+ "Lineout", "U19 OUTL",
+ "Lineout", "U19 OUTR";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_B>;
+ };
+ };
+
+ /* i2s jack output interface */
+ dai-link-7 {
+ sound-dai = <&tdmif_c>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_C>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-8 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ /* acodec glue */
+ dai-link-9 {
+ sound-dai = <&toacodec TOACODEC_OUT>;
+
+ codec {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddao_1v8>;
+ status = "okay";
+};
+
+&arb {
+ status = "okay";
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ /*
+ * WARNING: The USB Hub on the Odroid-N2 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+ linux,rc-map-name = "rc-odroid";
+};
+
+&pwm_ab {
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
+/*
+ * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
+ * and eMMC Data 4 to 7 pins.
+ * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
+ * and change bus-width to 4 then spifc can be enabled.
+ * The SW1 slide should also be set to the correct position.
+ */
+&spifc {
+ status = "disabled";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ mx25u64: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ };
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmif_c {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmin_lb {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&toacodec {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+ phy-supply = <&vcc_5v>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&hub_5v>;
+};
diff --git a/arch/arm/dts/meson-g12b-w400.dtsi b/arch/arm/dts/meson-g12b-w400.dtsi
new file mode 100644
index 0000000..2802ddb
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-w400.dtsi
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b.dtsi"
+#include "meson-g12b-s922x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ flash_1v8: regulator-flash_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "FLASH_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ main_12v: regulator-main_12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ };
+
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ regulator-always-on;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ /* FIXME: actually controlled by VDDCPU_B_EN */
+ };
+
+ vddcpu_a: regulator-vddcpu-a {
+ /*
+ * MP1653 Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_A";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&main_12v>;
+
+ pwms = <&pwm_ab 0 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddcpu_b: regulator-vddcpu-b {
+ /*
+ * MP1652 Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU_B";
+ regulator-min-microvolt = <721000>;
+ regulator-max-microvolt = <1022000>;
+
+ vin-supply = <&main_12v>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ usb1_pow: regulator-usb1-pow {
+ compatible = "regulator-fixed";
+ regulator-name = "USB1_POW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* connected to SY6280A Power Switch */
+ gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_pwr_en: regulator-usb-pwr-en {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v>;
+
+ /* Connected to USB3 Type-A Port power enable */
+ gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vddao_1v8: regulator-vddao-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&main_12v>;
+ regulator-always-on;
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+};
+
+&cec_AO {
+ pinctrl-0 = <&cec_ao_a_h_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cecb_AO {
+ pinctrl-0 = <&cec_ao_b_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu_b>;
+ operating-points-v2 = <&cpu_opp_table_0>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu100 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu101 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu102 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu103 {
+ cpu-supply = <&vddcpu_a>;
+ operating-points-v2 = <&cpub_opp_table_1>;
+ clocks = <&clkc CLKID_CPUB_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&vcc_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ab {
+ pinctrl-0 = <&pwm_a_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&pwm_ef {
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin0";
+ status = "okay";
+};
+
+/* SDIO */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_1v8>;
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddao_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&flash_1v8>;
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+ vbus-supply = <&usb_pwr_en>;
+};
+
+&usb2_phy0 {
+ phy-supply = <&usb1_pow>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&usb1_pow>;
+};
diff --git a/arch/arm/dts/meson-gx-mali450.dtsi b/arch/arm/dts/meson-gx-mali450.dtsi
new file mode 100644
index 0000000..f9771b5
--- /dev/null
+++ b/arch/arm/dts/meson-gx-mali450.dtsi
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/ {
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-285714285 {
+ opp-hz = /bits/ 64 <285714285>;
+ opp-microvolt = <950000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-666666666 {
+ opp-hz = /bits/ 64 <666666666>;
+ opp-microvolt = <950000>;
+ };
+ opp-744000000 {
+ opp-hz = /bits/ 64 <744000000>;
+ opp-microvolt = <950000>;
+ };
+ };
+};
+
+&apb {
+ mali: gpu@c0000 {
+ compatible = "arm,mali-450";
+ reg = <0x0 0xc0000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+};
diff --git a/arch/arm/dts/meson-gx-p23x-q20x.dtsi b/arch/arm/dts/meson-gx-p23x-q20x.dtsi
new file mode 100644
index 0000000..6b57e15
--- /dev/null
+++ b/arch/arm/dts/meson-gx-p23x-q20x.dtsi
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ */
+
+/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either
+ * the pin-compatible S912 (GXM) or S905D (GXL) SoCs.
+ */
+
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ dio2133: analog-amplifier {
+ compatible = "simple-audio-amplifier";
+ sound-name-prefix = "AU2";
+ VCC-supply = <&hdmi_5v>;
+ enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ };
+
+ spdif_dit: audio-codec-0 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ hdmi_5v: regulator-hdmi-5v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "HDMI_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "GX-P230-Q200";
+ audio-aux-devs = <&dio2133>;
+ audio-widgets = "Line", "Lineout";
+ audio-routing = "AU2 INL", "ACODEC LOLP",
+ "AU2 INR", "ACODEC LORP",
+ "AU2 INL", "ACODEC LOLN",
+ "AU2 INR", "ACODEC LORN",
+ "Lineout", "AU2 OUTL",
+ "Lineout", "AU2 OUTR";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+
+ codec-1 {
+ sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ dai-link-5 {
+ sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddio_ao18>;
+ status = "okay";
+};
+
+&aiu {
+ status = "okay";
+ pinctrl-0 = <&spdif_out_h_pins>;
+ pinctrl-names = "default";
+
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+ðmac {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&hdmi_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_ef {
+ status = "okay";
+ pinctrl-0 = <&pwm_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&clkc CLKID_FCLK_DIV4>;
+ clock-names = "clkin0";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "okay";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+
+ non-removable;
+ disable-wp;
+
+ /* WiFi firmware requires power to be kept while in suspend */
+ keep-power-in-suspend;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "otg";
+};
diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi
index ba63c36..0edd137 100644
--- a/arch/arm/dts/meson-gx.dtsi
+++ b/arch/arm/dts/meson-gx.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/meson-gxbb-power.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -60,7 +61,7 @@
compatible = "amlogic,simple-framebuffer",
"simple-framebuffer";
amlogic,pipeline = "vpu-cvbs";
- power-domains = <&pwrc_vpu>;
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
status = "disabled";
};
@@ -68,7 +69,7 @@
compatible = "amlogic,simple-framebuffer",
"simple-framebuffer";
amlogic,pipeline = "vpu-hdmi";
- power-domains = <&pwrc_vpu>;
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
status = "disabled";
};
};
@@ -438,12 +439,6 @@
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
- pwrc_vpu: power-controller-vpu {
- compatible = "amlogic,meson-gx-pwrc-vpu";
- #power-domain-cells = <0>;
- amlogic,hhi-sysctrl = <&sysctrl>;
- };
-
clkc_AO: clock-controller {
compatible = "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
@@ -552,6 +547,12 @@
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0 0 0 0x400>;
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson-gxbb-pwrc";
+ #power-domain-cells = <1>;
+ amlogic,ao-sysctrl = <&sysctrl_AO>;
+ };
};
mailbox: mailbox@404 {
@@ -574,6 +575,7 @@
interrupt-names = "macirq";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
+ power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>;
status = "disabled";
};
diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
index 234490d..7c029f5 100644
--- a/arch/arm/dts/meson-gxbb.dtsi
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -4,6 +4,7 @@
*/
#include "meson-gx.dtsi"
+#include "meson-gx-mali450.dtsi"
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>
@@ -264,46 +265,6 @@
};
};
-&apb {
- mali: gpu@c0000 {
- compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
- reg = <0x0 0xc0000 0x0 0x40000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp", "gpmmu", "pp", "pmu",
- "pp0", "ppmmu0", "pp1", "ppmmu1",
- "pp2", "ppmmu2";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- clock-names = "bus", "core";
-
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_GP0_PLL>,
- <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <0>, /* Do Nothing */
- <&clkc CLKID_GP0_PLL>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <744000000>,
- <0>, /* Do Nothing */
- <744000000>,
- <0>; /* Do Nothing */
- };
-};
-
&cbus {
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
@@ -333,8 +294,9 @@
ðmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
};
&gpio_intc {
@@ -385,6 +347,16 @@
clocks = <&clkc CLKID_I2C>;
};
+&mali {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ assigned-clocks = <&clkc CLKID_GP0_PLL>;
+ assigned-clock-rates = <744000000>;
+};
+
&periphs {
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
@@ -747,7 +719,7 @@
};
};
-&pwrc_vpu {
+&pwrc {
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
@@ -760,6 +732,9 @@
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
+ reset-names = "viu", "venc", "vcbus", "bt656",
+ "dvin", "rdma", "venci", "vencp",
+ "vdac", "vdi6", "vencl", "vid_lock";
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
@@ -866,7 +841,7 @@
&vpu {
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
- power-domains = <&pwrc_vpu>;
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
};
&vdec {
diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi
index 6aaafff..478e755 100644
--- a/arch/arm/dts/meson-gxl-mali.dtsi
+++ b/arch/arm/dts/meson-gxl-mali.dtsi
@@ -4,42 +4,14 @@
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
-&apb {
- mali: gpu@c0000 {
- compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
- reg = <0x0 0xc0000 0x0 0x40000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp", "gpmmu", "pp", "pmu",
- "pp0", "ppmmu0", "pp1", "ppmmu1",
- "pp2", "ppmmu2";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- clock-names = "bus", "core";
+#include "meson-gx-mali450.dtsi"
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_GP0_PLL>,
- <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <0>, /* Do Nothing */
- <&clkc CLKID_GP0_PLL>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <744000000>,
- <0>, /* Do Nothing */
- <744000000>,
- <0>; /* Do Nothing */
- };
+&mali {
+ compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
+
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+ clock-names = "bus", "core";
+
+ assigned-clocks = <&clkc CLKID_GP0_PLL>;
+ assigned-clock-rates = <744000000>;
};
diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
index 6a226fa..9e43f4d 100644
--- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
+++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
@@ -10,7 +10,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/sound/meson-aiu.h>
-#include "meson-gxl-s905x.dtsi"
+#include "meson-gxl-s805x.dtsi"
/ {
compatible = "libretech,aml-s805x-ac", "amlogic,s805x",
diff --git a/arch/arm/dts/meson-gxl-s805x.dtsi b/arch/arm/dts/meson-gxl-s805x.dtsi
new file mode 100644
index 0000000..2997584
--- /dev/null
+++ b/arch/arm/dts/meson-gxl-s805x.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible = "amlogic,s805x", "amlogic,meson-gxl";
+};
+
+/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */
+&gpu_opp_table {
+ opp-744000000 {
+ status = "disabled";
+ };
+};
+
+&mali {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+};
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi
new file mode 100644
index 0000000..8ff5a0e
--- /dev/null
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#include "meson-gxl-u-boot.dtsi"
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
new file mode 100644
index 0000000..675eaa8
--- /dev/null
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x",
+ "amlogic,meson-gxl";
+ model = "Libre Computer AML-S905X-CC V2";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+
+ led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+
+ vcck: regulator-vcck {
+ compatible = "regulator-fixed";
+ regulator-name = "VCCK";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vcc_card: regulator-vcc_card {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_CARD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vddio_ao3v3>;
+
+ gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc5v: regulator-vcc5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&ao_5v>;
+
+ gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>;
+ };
+
+ vddio_ao3v3: regulator-vddio_ao3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+
+ vddio_card: regulator-vddio-card {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_CARD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+
+ regulator-settling-time-up-us = <200>;
+ regulator-settling-time-down-us = <50000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddio_ao3v3>;
+ regulator-always-on;
+ };
+
+ vcc_1v8: regulator-vcc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC 1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddio_ao3v3>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "GXL-LIBRETECH-S905X-CC-V2";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+
+&aiu {
+ status = "okay";
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+
+ðmac {
+ status = "okay";
+};
+
+&internal_phy {
+ pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
+ pinctrl-names = "default";
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ hdmi-supply = <&vcc5v>;
+ pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vcc_card>;
+ vqmmc-supply = <&vddio_card>;
+
+ status = "okay";
+};
+
+/* eMMC */
+&sd_emmc_c {
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddio_ao3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+
+ status = "okay";
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ nor_4u1: spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <3000000>;
+ };
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy0 {
+ pinctrl-names = "default";
+ phy-supply = <&vcc5v>;
+};
+
+&usb2_phy1 {
+ phy-supply = <&vcc5v>;
+};
diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi
index fc59c85..c3ac531 100644
--- a/arch/arm/dts/meson-gxl.dtsi
+++ b/arch/arm/dts/meson-gxl.dtsi
@@ -131,8 +131,9 @@
ðmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
mdio0: mdio {
#address-cells = <1>;
@@ -337,6 +338,11 @@
};
};
+&hwrng {
+ clocks = <&clkc CLKID_RNG0>;
+ clock-names = "core";
+};
+
&i2c_A {
clocks = <&clkc CLKID_I2C>;
};
@@ -782,7 +788,7 @@
};
};
-&pwrc_vpu {
+&pwrc {
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_VCBUS>,
@@ -795,6 +801,9 @@
<&reset RESET_VDI6>,
<&reset RESET_VENCL>,
<&reset RESET_VID_LOCK>;
+ reset-names = "viu", "venc", "vcbus", "bt656",
+ "dvin", "rdma", "venci", "vencp",
+ "vdac", "vdi6", "vencl", "vid_lock";
clocks = <&clkc CLKID_VPU>,
<&clkc CLKID_VAPB>;
clock-names = "vpu", "vapb";
@@ -901,7 +910,7 @@
&vpu {
compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
- power-domains = <&pwrc_vpu>;
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
};
&vdec {
diff --git a/arch/arm/dts/meson-gxm-wetek-core2-u-boot.dtsi b/arch/arm/dts/meson-gxm-wetek-core2-u-boot.dtsi
new file mode 100644
index 0000000..39270ea
--- /dev/null
+++ b/arch/arm/dts/meson-gxm-wetek-core2-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-gxl-u-boot.dtsi"
diff --git a/arch/arm/dts/meson-gxm-wetek-core2.dts b/arch/arm/dts/meson-gxm-wetek-core2.dts
new file mode 100644
index 0000000..ec794c1
--- /dev/null
+++ b/arch/arm/dts/meson-gxm-wetek-core2.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm";
+ model = "WeTek Core 2";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-update {
+ label = "update";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <100>;
+
+ button-power {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* Disabled as Realtek RTL8152 USB provides Ethernet */
+ðmac {
+ status = "disabled";
+};
+
+&internal_phy {
+ status = "disabled";
+};
+
+&ir {
+ linux,rc-map-name = "rc-wetek-play2";
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi
index 40e3e12..fe41451 100644
--- a/arch/arm/dts/meson-gxm.dtsi
+++ b/arch/arm/dts/meson-gxm.dtsi
@@ -82,6 +82,35 @@
#cooling-cells = <2>;
};
};
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-285714285 {
+ opp-hz = /bits/ 64 <285714285>;
+ opp-microvolt = <950000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-666666666 {
+ opp-hz = /bits/ 64 <666666666>;
+ opp-microvolt = <950000>;
+ };
+ };
};
&apb {
@@ -106,21 +135,7 @@
interrupt-names = "job", "mmu", "gpu";
clocks = <&clkc CLKID_MALI>;
resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
-
- /*
- * Mali clocking is provided by two identical clock paths
- * MALI_0 and MALI_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- */
- assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
- <&clkc CLKID_MALI_0>,
- <&clkc CLKID_MALI>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
- <0>, /* Do Nothing */
- <&clkc CLKID_MALI_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
- <0>; /* Do Nothing */
+ operating-points-v2 = <&gpu_opp_table>;
};
};
diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
index 94f75b4..7b46555 100644
--- a/arch/arm/dts/meson-khadas-vim3.dtsi
+++ b/arch/arm/dts/meson-khadas-vim3.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
aliases {
@@ -41,13 +42,13 @@
led-white {
label = "vim3:white:sys";
- gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-red {
label = "vim3:red";
- gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>;
};
};
@@ -161,6 +162,62 @@
};
};
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "G12B-KHADAS-VIM3";
+ audio-aux-devs = <&tdmout_a>;
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 0",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 0",
+ "TDM_A Playback", "TDMOUT_A OUT";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_a>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-4 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
@@ -169,6 +226,14 @@
};
};
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
&cec_AO {
pinctrl-0 = <&cec_ao_a_h_pins>;
pinctrl-names = "default";
@@ -221,6 +286,18 @@
amlogic,tx-delay-ns = <2>;
};
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
@@ -368,6 +445,19 @@
};
};
+
+&tdmif_a {
+ status = "okay";
+};
+
+&tdmout_a {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l.dts b/arch/arm/dts/meson-sm1-khadas-vim3l.dts
index 0da56c0..4b517ca 100644
--- a/arch/arm/dts/meson-sm1-khadas-vim3l.dts
+++ b/arch/arm/dts/meson-sm1-khadas-vim3l.dts
@@ -32,69 +32,6 @@
regulator-boot-on;
regulator-always-on;
};
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "SM1-KHADAS-VIM3L";
- audio-aux-devs = <&tdmout_a>;
- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
- "TDMOUT_A IN 1", "FRDDR_B OUT 0",
- "TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_a>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
};
&cpu0 {
@@ -125,18 +62,6 @@
clock-latency = <50000>;
};
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
&pwm_AO_cd {
pinctrl-0 = <&pwm_ao_d_e_pins>;
pinctrl-names = "default";
@@ -174,14 +99,3 @@
};
*/
-&tdmif_a {
- status = "okay";
-};
-
-&tdmout_a {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi
index 897c421..3b080ac 100644
--- a/arch/arm/dts/stih410-b2260-u-boot.dtsi
+++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*
*/
diff --git a/arch/arm/dts/stih410-b2260.dts b/arch/arm/dts/stih410-b2260.dts
index 4fbd8e9..8c4155b 100644
--- a/arch/arm/dts/stih410-b2260.dts
+++ b/arch/arm/dts/stih410-b2260.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 STMicroelectronics (R&D) Limited.
- * Author: Patrice Chotard <patrice.chotard@st.com>
+ * Author: Patrice Chotard <patrice.chotard@foss.st.com>
*/
/dts-v1/;
#include "stih410.dtsi"
diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi
index e75cf99..09d9d9a 100644
--- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/memory/stm32-sdram.h>
diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
index df99e01..297cc56 100644
--- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/memory/stm32-sdram.h>
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
index 7223ba4..9eda8f5 100644
--- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/memory/stm32-sdram.h>
diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts
index 8100716..7927310 100644
--- a/arch/arm/dts/stm32h743i-disco.dts
+++ b/arch/arm/dts/stm32h743i-disco.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2017 - Patrice Chotard <patrice.chotard@st.com>
+ * Copyright 2017 - Patrice Chotard <patrice.chotard@foss.st.com>
*
*/
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 92345b7..6868769 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -72,8 +72,8 @@
&pinctrl {
/* These should bound to FMC2 bus driver, but we do not have one */
- pinctrl-0 = <&fmc_pins_b>;
- pinctrl-1 = <&fmc_sleep_pins_b>;
+ pinctrl-0 = <&fmc_pins_b &mco2_pins_a>;
+ pinctrl-1 = <&fmc_sleep_pins_b &mco2_sleep_pins_a>;
pinctrl-names = "default", "sleep";
fmc_pins_b: fmc-0 {
@@ -130,6 +130,21 @@
<STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
};
};
+
+ mco2_pins_a: mco2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ mco2_sleep_pins_a: mco2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
+ };
+ };
};
&pmic {
@@ -181,7 +196,7 @@
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
- CLK_MCO2_DISABLED
+ CLK_MCO2_PLL4P
>;
st,clkdiv = <
@@ -195,7 +210,7 @@
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
- 0 /*MCO2*/
+ 1 /*MCO2*/
>;
st,pkcs = <
@@ -258,7 +273,7 @@
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = < 1 49 11 11 11 PQR(1,1,1) >;
+ cfg = < 1 49 5 11 11 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
index dafcce4..a1d1b8d 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@@ -58,7 +58,6 @@
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
- st,eth_ref_clk_sel;
phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
mdio0 {
@@ -267,7 +266,7 @@
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
- <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
bias-disable;
diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h
index a90fe55..c67d12d 100644
--- a/arch/arm/include/asm/arch-meson/boot.h
+++ b/arch/arm/include/asm/arch-meson/boot.h
@@ -7,6 +7,8 @@
#ifndef __MESON_BOOT_H__
#define __MESON_BOOT_H__
+#include <linux/types.h>
+
/* Boot device */
#define BOOT_DEVICE_RESERVED 0
#define BOOT_DEVICE_EMMC 1
@@ -17,4 +19,6 @@
int meson_get_boot_device(void);
+int meson_get_soc_rev(char *buff, size_t buff_len);
+
#endif /* __MESON_BOOT_H__ */
diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c
index e61d1ad..90e7dfa 100644
--- a/arch/arm/mach-meson/board-info.c
+++ b/arch/arm/mach-meson/board-info.c
@@ -131,7 +131,7 @@
printf("Model: %s\n", model ? model : "Unknown");
}
-int show_board_info(void)
+static unsigned int get_socinfo(void)
{
struct regmap *regmap;
int nodeoffset, ret;
@@ -163,8 +163,20 @@
return 0;
}
+ return socinfo;
+}
+
+int show_board_info(void)
+{
+ unsigned int socinfo;
+
/* print board information */
print_board_model();
+
+ socinfo = get_socinfo();
+ if (!socinfo)
+ return 0;
+
printf("SoC: Amlogic Meson %s (%s) Revision %x:%x (%x:%x)\n",
socinfo_to_soc_id(socinfo),
socinfo_to_package_id(socinfo),
@@ -175,3 +187,15 @@
return 0;
}
+
+int meson_get_soc_rev(char *buff, size_t buff_len)
+{
+ unsigned int socinfo;
+
+ socinfo = get_socinfo();
+ if (!socinfo)
+ return -1;
+
+ /* Write SoC info */
+ return snprintf(buff, buff_len, "%x", socinfo_to_minor(socinfo));
+}
diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c
index 37ee9e1..13322e3 100644
--- a/arch/arm/mach-stm32mp/boot_params.c
+++ b/arch/arm/mach-stm32mp/boot_params.c
@@ -3,6 +3,8 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY LOGC_ARCH
+
#include <common.h>
#include <log.h>
#include <asm/sections.h>
@@ -32,15 +34,15 @@
*/
void *board_fdt_blob_setup(void)
{
- debug("%s: nt_fw_dtb=%lx\n", __func__, nt_fw_dtb);
+ log_debug("%s: nt_fw_dtb=%lx\n", __func__, nt_fw_dtb);
/* use external device tree only if address is valid */
if (nt_fw_dtb >= STM32_DDR_BASE) {
if (fdt_magic(nt_fw_dtb) == FDT_MAGIC)
return (void *)nt_fw_dtb;
- debug("%s: DTB not found.\n", __func__);
+ log_debug("%s: DTB not found.\n", __func__);
}
- debug("%s: fall back to builtin DTB, %p\n", __func__, &_end);
+ log_debug("%s: fall back to builtin DTB, %p\n", __func__, &_end);
return (void *)&_end;
}
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 84e0bdd..88c7aec 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_MISC
+
#include <common.h>
#include <dm.h>
#include <log.h>
@@ -10,6 +12,7 @@
#include <asm/io.h>
#include <asm/arch/bsec.h>
#include <asm/arch/stm32mp1_smc.h>
+#include <dm/device_compat.h>
#include <linux/arm-smccc.h>
#include <linux/iopoll.h>
@@ -160,7 +163,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_shadow_register(u32 base, u32 otp)
+static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
{
u32 val;
int ret;
@@ -168,7 +171,8 @@
/* check if shadowing of otp is locked */
if (bsec_read_SR_lock(base, otp))
- pr_debug("bsec : OTP %d is locked and refreshed with 0\n", otp);
+ dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
+ otp);
/* check if safemem is power up */
val = readl(base + BSEC_OTP_STATUS_OFF);
@@ -203,7 +207,7 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_read_shadow(u32 base, u32 *val, u32 otp)
+static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
{
*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
@@ -217,11 +221,11 @@
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_write_shadow(u32 base, u32 val, u32 otp)
+static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
{
/* check if programming of otp is locked */
if (bsec_read_SW_lock(base, otp))
- pr_debug("bsec : OTP %d is lock, write will be ignore\n", otp);
+ dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);
writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
@@ -236,16 +240,16 @@
* after the function the otp data is not refreshed in shadow
* Return: 0 if no error
*/
-static int bsec_program_otp(long base, u32 val, u32 otp)
+static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
{
u32 ret;
bool power_up = false;
if (bsec_read_SP_lock(base, otp))
- pr_debug("bsec : OTP %d locked, prog will be ignore\n", otp);
+ dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);
if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
- pr_debug("bsec : Global lock, prog will be ignore\n");
+ dev_dbg(dev, "Global lock, prog will be ignore\n");
/* check if safemem is power up */
if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
@@ -298,21 +302,21 @@
plat = dev_get_plat(dev);
/* read current shadow value */
- ret = bsec_read_shadow(plat->base, &tmp_data, otp);
+ ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
if (ret)
return ret;
/* copy otp in shadow */
- ret = bsec_shadow_register(plat->base, otp);
+ ret = bsec_shadow_register(dev, plat->base, otp);
if (ret)
return ret;
- ret = bsec_read_shadow(plat->base, val, otp);
+ ret = bsec_read_shadow(dev, plat->base, val, otp);
if (ret)
return ret;
/* restore shadow value */
- ret = bsec_write_shadow(plat->base, tmp_data, otp);
+ ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);
return ret;
}
@@ -328,7 +332,7 @@
plat = dev_get_plat(dev);
- return bsec_read_shadow(plat->base, val, otp);
+ return bsec_read_shadow(dev, plat->base, val, otp);
}
static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
@@ -352,7 +356,7 @@
plat = dev_get_plat(dev);
- return bsec_program_otp(plat->base, val, otp);
+ return bsec_program_otp(dev, plat->base, val, otp);
}
@@ -367,7 +371,7 @@
plat = dev_get_plat(dev);
- return bsec_write_shadow(plat->base, val, otp);
+ return bsec_write_shadow(dev, plat->base, val, otp);
}
static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
@@ -497,7 +501,7 @@
for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
if (!bsec_read_SR_lock(plat->base, otp))
- bsec_shadow_register(plat->base, otp);
+ bsec_shadow_register(dev, plat->base, otp);
}
return 0;
@@ -527,7 +531,7 @@
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stm32mp_bsec), &dev);
if (ret || !dev) {
- pr_debug("bsec driver not available\n");
+ log_debug("bsec driver not available\n");
return false;
}
diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
index 544bab3..42fdc11 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <command.h>
#include <console.h>
+#include <log.h>
#include <misc.h>
#include <dm/device.h>
#include <dm/uclass.h>
@@ -34,7 +35,7 @@
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret) {
- pr_err("Can't find stm32mp_bsec driver\n");
+ log_err("Can't find stm32mp_bsec driver\n");
return;
}
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
index 49dd25b..34a6be6 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
@@ -56,7 +56,7 @@
link = LINK_SERIAL;
if (link == LINK_UNDEFINED) {
- pr_err("not supported link=%s\n", argv[1]);
+ log_err("not supported link=%s\n", argv[1]);
return CMD_RET_USAGE;
}
@@ -90,7 +90,7 @@
data = (struct stm32prog_data *)malloc(sizeof(*data));
if (!data) {
- pr_err("Alloc failed.");
+ log_err("Alloc failed.");
return CMD_RET_FAILURE;
}
stm32prog_data = data;
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index fc9a2af..a8e7158 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -97,28 +97,28 @@
header->image_length = 0x0;
if (!raw_header || !header) {
- pr_debug("%s:no header data\n", __func__);
+ log_debug("%s:no header data\n", __func__);
return -1;
}
if (raw_header->magic_number !=
(('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) {
- pr_debug("%s:invalid magic number : 0x%x\n",
- __func__, raw_header->magic_number);
+ log_debug("%s:invalid magic number : 0x%x\n",
+ __func__, raw_header->magic_number);
return -2;
}
/* only header v1.0 supported */
if (raw_header->header_version != 0x00010000) {
- pr_debug("%s:invalid header version : 0x%x\n",
- __func__, raw_header->header_version);
+ log_debug("%s:invalid header version : 0x%x\n",
+ __func__, raw_header->header_version);
return -3;
}
if (raw_header->reserved1 != 0x0 || raw_header->reserved2) {
- pr_debug("%s:invalid reserved field\n", __func__);
+ log_debug("%s:invalid reserved field\n", __func__);
return -4;
}
for (i = 0; i < (sizeof(raw_header->padding) / 4); i++) {
if (raw_header->padding[i] != 0) {
- pr_debug("%s:invalid padding field\n", __func__);
+ log_debug("%s:invalid padding field\n", __func__);
return -5;
}
}
@@ -376,7 +376,7 @@
last = start + size;
*last = 0x0; /* force null terminated string */
- pr_debug("flash layout =\n%s\n", start);
+ log_debug("flash layout =\n%s\n", start);
/* calculate expected number of partitions */
part_list_size = 1;
@@ -584,11 +584,11 @@
last_addr = (u64)(block_dev->lba - GPT_HEADER_SZ - 1) *
block_dev->blksz;
}
- pr_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id,
- block_dev->lba, block_dev->blksz);
- pr_debug(" available address = 0x%llx..0x%llx\n",
- first_addr, last_addr);
- pr_debug(" full_update = %d\n", dev->full_update);
+ log_debug("MMC %d: lba=%ld blksz=%ld\n", dev->dev_id,
+ block_dev->lba, block_dev->blksz);
+ log_debug(" available address = 0x%llx..0x%llx\n",
+ first_addr, last_addr);
+ log_debug(" full_update = %d\n", dev->full_update);
break;
case STM32PROG_NOR:
case STM32PROG_NAND:
@@ -598,7 +598,7 @@
return -ENODEV;
}
get_mtd_by_target(mtd_id, dev->target, dev->dev_id);
- pr_debug("%s\n", mtd_id);
+ log_debug("%s\n", mtd_id);
mtdparts_init();
mtd = get_mtd_device_nm(mtd_id);
@@ -609,10 +609,10 @@
first_addr = 0;
last_addr = mtd->size;
dev->erase_size = mtd->erasesize;
- pr_debug("MTD device %s: size=%lld erasesize=%d\n",
- mtd_id, mtd->size, mtd->erasesize);
- pr_debug(" available address = 0x%llx..0x%llx\n",
- first_addr, last_addr);
+ log_debug("MTD device %s: size=%lld erasesize=%d\n",
+ mtd_id, mtd->size, mtd->erasesize);
+ log_debug(" available address = 0x%llx..0x%llx\n",
+ first_addr, last_addr);
dev->mtd = mtd;
break;
case STM32PROG_RAM:
@@ -624,13 +624,13 @@
stm32prog_err("unknown device type = %d", dev->target);
return -ENODEV;
}
- pr_debug(" erase size = 0x%x\n", dev->erase_size);
- pr_debug(" full_update = %d\n", dev->full_update);
+ log_debug(" erase size = 0x%x\n", dev->erase_size);
+ log_debug(" full_update = %d\n", dev->full_update);
/* order partition list in offset order */
list_sort(NULL, &dev->part_list, &part_cmp);
part_id = 1;
- pr_debug("id : Opt Phase Name target.n dev.n addr size part_off part_size\n");
+ log_debug("id : Opt Phase Name target.n dev.n addr size part_off part_size\n");
list_for_each_entry(part, &dev->part_list, list) {
if (part->bin_nb > 1) {
if ((dev->target != STM32PROG_NAND &&
@@ -650,10 +650,10 @@
part->size = block_dev->lba * block_dev->blksz;
else
part->size = last_addr;
- pr_debug("-- : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx\n",
- part->option, part->id, part->name,
- part->part_type, part->bin_nb, part->target,
- part->dev_id, part->addr, part->size);
+ log_debug("-- : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx\n",
+ part->option, part->id, part->name,
+ part->part_type, part->bin_nb, part->target,
+ part->dev_id, part->addr, part->size);
continue;
}
if (part->part_id < 0) { /* boot hw partition for eMMC */
@@ -709,10 +709,10 @@
part->dev->erase_size);
return -EINVAL;
}
- pr_debug("%02d : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx",
- part->part_id, part->option, part->id, part->name,
- part->part_type, part->bin_nb, part->target,
- part->dev_id, part->addr, part->size);
+ log_debug("%02d : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx",
+ part->part_id, part->option, part->id, part->name,
+ part->part_type, part->bin_nb, part->target,
+ part->dev_id, part->addr, part->size);
part_addr = 0;
part_size = 0;
@@ -726,7 +726,7 @@
* created for full update
*/
if (dev->full_update || part->part_id < 0) {
- pr_debug("\n");
+ log_debug("\n");
continue;
}
struct disk_partition partinfo;
@@ -770,11 +770,11 @@
/* no partition for this device */
if (!part_found) {
- pr_debug("\n");
+ log_debug("\n");
continue;
}
- pr_debug(" %08llx %08llx\n", part_addr, part_size);
+ log_debug(" %08llx %08llx\n", part_addr, part_size);
if (part->addr != part_addr) {
stm32prog_err("%s (0x%x): Bad address for partition %d (%s) = 0x%llx <> 0x%llx expected",
@@ -910,8 +910,8 @@
continue;
if (offset + 100 > buflen) {
- pr_debug("\n%s: buffer too small, %s skippped",
- __func__, part->name);
+ log_debug("\n%s: buffer too small, %s skippped",
+ __func__, part->name);
continue;
}
@@ -959,7 +959,7 @@
if (offset) {
offset += snprintf(buf + offset, buflen - offset, "\"");
- pr_debug("\ncmd: %s\n", buf);
+ log_debug("\ncmd: %s\n", buf);
if (run_command(buf, 0)) {
stm32prog_err("GPT partitionning fail: %s",
buf);
@@ -974,7 +974,7 @@
#ifdef DEBUG
sprintf(buf, "gpt verify mmc %d", data->dev[i].dev_id);
- pr_debug("\ncmd: %s", buf);
+ log_debug("\ncmd: %s", buf);
if (run_command(buf, 0))
printf("fail !\n");
else
@@ -1098,10 +1098,10 @@
stm32prog_err("invalid target: %d", part->target);
return ret;
}
- pr_debug("dfu_alt_add(%s,%s,%s)\n", dfustr, devstr, buf);
+ log_debug("dfu_alt_add(%s,%s,%s)\n", dfustr, devstr, buf);
ret = dfu_alt_add(dfu, dfustr, devstr, buf);
- pr_debug("dfu_alt_add(%s,%s,%s) result %d\n",
- dfustr, devstr, buf, ret);
+ log_debug("dfu_alt_add(%s,%s,%s) result %d\n",
+ dfustr, devstr, buf, ret);
return ret;
}
@@ -1116,7 +1116,7 @@
sprintf(devstr, "%d", phase);
sprintf(buf, "@%s/0x%02x/1*%dBe", name, phase, size);
ret = dfu_alt_add(dfu, "virt", devstr, buf);
- pr_debug("dfu_alt_add(virt,%s,%s) result %d\n", devstr, buf, ret);
+ log_debug("dfu_alt_add(virt,%s,%s) result %d\n", devstr, buf, ret);
return ret;
}
@@ -1171,7 +1171,7 @@
sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000",
PHASE_FLASHLAYOUT, STM32_DDR_BASE);
ret = dfu_alt_add(dfu, "ram", NULL, buf);
- pr_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret);
+ log_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret);
}
if (!ret)
@@ -1196,7 +1196,7 @@
int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
long *size)
{
- pr_debug("%s: %x %lx\n", __func__, offset, *size);
+ log_debug("%s: %x %lx\n", __func__, offset, *size);
if (!data->otp_part) {
data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, OTP_SIZE);
@@ -1226,7 +1226,7 @@
return -1;
}
- pr_debug("%s: %x %lx\n", __func__, offset, *size);
+ log_debug("%s: %x %lx\n", __func__, offset, *size);
/* alway read for first packet */
if (!offset) {
if (!data->otp_part)
@@ -1258,7 +1258,7 @@
memcpy(buffer, (void *)((u32)data->otp_part + offset), *size);
end_otp_read:
- pr_debug("%s: result %i\n", __func__, result);
+ log_debug("%s: result %i\n", __func__, result);
return result;
}
@@ -1292,20 +1292,20 @@
result = 0;
break;
default:
- pr_err("%s: OTP incorrect value (err = %ld)\n",
- __func__, res.a1);
+ log_err("%s: OTP incorrect value (err = %ld)\n",
+ __func__, res.a1);
result = -EINVAL;
break;
}
} else {
- pr_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n",
- __func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0);
+ log_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n",
+ __func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0);
result = -EINVAL;
}
free(data->otp_part);
data->otp_part = NULL;
- pr_debug("%s: result %i\n", __func__, result);
+ log_debug("%s: result %i\n", __func__, result);
return result;
}
@@ -1313,7 +1313,7 @@
int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
long *size)
{
- pr_debug("%s: %x %lx\n", __func__, offset, *size);
+ log_debug("%s: %x %lx\n", __func__, offset, *size);
if (!offset)
memset(data->pmic_part, 0, PMIC_SIZE);
@@ -1338,7 +1338,7 @@
return -EOPNOTSUPP;
}
- pr_debug("%s: %x %lx\n", __func__, offset, *size);
+ log_debug("%s: %x %lx\n", __func__, offset, *size);
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stpmic1_nvm),
&dev);
@@ -1373,7 +1373,7 @@
memcpy(buffer, &data->pmic_part[offset], *size);
end_pmic_read:
- pr_debug("%s: result %i\n", __func__, result);
+ log_debug("%s: result %i\n", __func__, result);
return result;
}
@@ -1429,7 +1429,7 @@
if (!fsbl)
return -ENOMEM;
ret = dfu->read_medium(dfu, 0, fsbl, &size);
- pr_debug("%s read size=%lx ret=%d\n", __func__, size, ret);
+ log_debug("%s read size=%lx ret=%d\n", __func__, size, ret);
if (ret)
goto error;
@@ -1439,8 +1439,8 @@
offset += size;
/* write to the next erase block */
ret = dfu->write_medium(dfu, offset, fsbl, &size);
- pr_debug("%s copy at ofset=%lx size=%lx ret=%d",
- __func__, offset, size, ret);
+ log_debug("%s copy at ofset=%lx size=%lx ret=%d",
+ __func__, offset, size, ret);
if (ret)
goto error;
}
@@ -1751,6 +1751,6 @@
if (dfu->alt == stm32prog_data->cur_part->alt_id) {
dfu->offset = stm32prog_data->offset;
stm32prog_data->dfu_seq = 0;
- pr_debug("dfu offset = 0x%llx\n", dfu->offset);
+ log_debug("dfu offset = 0x%llx\n", dfu->offset);
}
}
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
index bae4e91..be482c3 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
@@ -172,7 +172,7 @@
if (data->phase != PHASE_RESET) { \
sprintf(data->error, args); \
data->phase = PHASE_RESET; \
- pr_err("Error: %s\n", data->error); } \
+ log_err("Error: %s\n", data->error); } \
}
/* Main function */
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
index 8aad4be..68d841b 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
@@ -159,8 +159,8 @@
dfu_entity->offset = offset;
data->offset = offset;
data->read_phase = phase;
- pr_debug("\nSTM32 download read %s offset=0x%x\n",
- dfu_entity->name, offset);
+ log_debug("\nSTM32 download read %s offset=0x%x\n",
+ dfu_entity->name, offset);
ret = dfu_read(dfu_entity, buffer, buffer_size,
dfu_entity->i_blk_seq_num);
if (ret < 0) {
@@ -198,7 +198,7 @@
sprintf(alias, "serial%d", link_dev);
path = fdt_get_alias(gd->fdt_blob, alias);
if (!path) {
- pr_err("%s alias not found", alias);
+ log_err("%s alias not found", alias);
return -ENODEV;
}
node = fdt_path_offset(gd->fdt_blob, path);
@@ -212,7 +212,7 @@
down_serial_dev = dev;
}
if (!down_serial_dev) {
- pr_err("%s = %s device not found", alias, path);
+ log_err("%s = %s device not found", alias, path);
return -ENODEV;
}
@@ -225,11 +225,11 @@
ops = serial_get_ops(down_serial_dev);
if (!ops) {
- pr_err("%s = %s missing ops", alias, path);
+ log_err("%s = %s missing ops", alias, path);
return -ENODEV;
}
if (!ops->setconfig) {
- pr_err("%s = %s missing setconfig", alias, path);
+ log_err("%s = %s missing setconfig", alias, path);
return -ENODEV;
}
@@ -397,14 +397,13 @@
if (!dfu_entity)
return -ENODEV;
- if (data->dfu_seq) {
- ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq);
- data->dfu_seq = 0;
- if (ret) {
- stm32prog_err("DFU flush failed [%d]", ret);
- return ret;
- }
+ ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq);
+ if (ret) {
+ stm32prog_err("DFU flush failed [%d]", ret);
+ return ret;
}
+ data->dfu_seq = 0;
+
printf("\n received length = 0x%x\n", data->cursor);
if (data->header.present) {
if (data->cursor !=
@@ -815,7 +814,7 @@
if (data->cursor >
image_header->image_length + BL_HEADER_SIZE) {
- pr_err("expected size exceeded\n");
+ log_err("expected size exceeded\n");
result = ABORT_BYTE;
goto end;
}
@@ -859,8 +858,8 @@
rcv_data = stm32prog_serial_getc();
if (rcv_data != tmp_xor) {
- pr_debug("1st checksum received = %x, computed %x\n",
- rcv_data, tmp_xor);
+ log_debug("1st checksum received = %x, computed %x\n",
+ rcv_data, tmp_xor);
goto error;
}
stm32prog_serial_putc(ACK_BYTE);
@@ -872,12 +871,12 @@
rcv_data = stm32prog_serial_getc();
if ((rcv_data ^ tmp_xor) != 0xFF) {
- pr_debug("2nd checksum received = %x, computed %x\n",
- rcv_data, tmp_xor);
+ log_debug("2nd checksum received = %x, computed %x\n",
+ rcv_data, tmp_xor);
goto error;
}
- pr_debug("%s : %x\n", __func__, part_id);
+ log_debug("%s : %x\n", __func__, part_id);
rcv_data = 0;
switch (part_id) {
case PHASE_OTP:
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
index 30547f9..bc44d9f 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
@@ -47,11 +47,11 @@
int ret;
if (*len < 5) {
- pr_err("size not allowed\n");
+ log_err("size not allowed\n");
return -EINVAL;
}
if (offset) {
- pr_err("invalid offset\n");
+ log_err("invalid offset\n");
return -EINVAL;
}
phase = pt[0];
@@ -66,7 +66,7 @@
/* set phase and offset */
ret = stm32prog_set_phase(stm32prog_data, phase, address);
if (ret)
- pr_err("failed: %d\n", ret);
+ log_err("failed: %d\n", ret);
return ret;
}
@@ -81,7 +81,7 @@
int length;
if (*len < PHASE_MIN_SIZE) {
- pr_err("request exceeds allowed area\n");
+ log_err("request exceeds allowed area\n");
return -EINVAL;
}
if (offset) {
@@ -171,8 +171,8 @@
{
if (dfu->dev_type != DFU_DEV_VIRT) {
*size = 0;
- pr_debug("%s, invalid dev_type = %d\n",
- __func__, dfu->dev_type);
+ log_debug("%s, invalid dev_type = %d\n",
+ __func__, dfu->dev_type);
return -EINVAL;
}
@@ -227,6 +227,6 @@
int g_dnl_get_board_bcd_device_number(int gcnum)
{
- pr_debug("%s\n", __func__);
+ log_debug("%s\n", __func__);
return 0x200;
}
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 29c0d92..717f80e 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+
+#define LOG_CATEGORY LOGC_ARCH
+
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
@@ -463,8 +466,8 @@
struct udevice *dev;
int alias;
- pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
- __func__, boot_ctx, boot_mode, instance, forced_mode);
+ log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
+ __func__, boot_ctx, boot_mode, instance, forced_mode);
switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
case BOOT_SERIAL_UART:
if (instance > ARRAY_SIZE(serial_addr))
@@ -510,7 +513,7 @@
env_set("boot_instance", "0");
break;
default:
- pr_debug("unexpected boot mode = %x\n", boot_mode);
+ log_debug("unexpected boot mode = %x\n", boot_mode);
break;
}
@@ -537,7 +540,7 @@
case BOOT_NORMAL:
break;
default:
- pr_debug("unexpected forced boot mode = %x\n", forced_mode);
+ log_debug("unexpected forced boot mode = %x\n", forced_mode);
break;
}
@@ -577,14 +580,13 @@
enetaddr[i] = ((uint8_t *)&otp)[i];
if (!is_valid_ethaddr(enetaddr)) {
- pr_err("invalid MAC address in OTP %pM\n", enetaddr);
+ log_err("invalid MAC address in OTP %pM\n", enetaddr);
return -EINVAL;
}
- pr_debug("OTP MAC address = %pM\n", enetaddr);
+ log_debug("OTP MAC address = %pM\n", enetaddr);
ret = eth_env_set_enetaddr("ethaddr", enetaddr);
if (ret)
- pr_err("Failed to set mac address %pM from OTP: %d\n",
- enetaddr, ret);
+ log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
#endif
return 0;
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 0e8ce63..32b177b 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY LOGC_ARCH
+
#include <common.h>
#include <dm.h>
#include <image.h>
@@ -21,15 +23,15 @@
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- debug("RAM init failed: %d\n", ret);
+ log_debug("RAM init failed: %d\n", ret);
return ret;
}
ret = ram_get_info(dev, &ram);
if (ret) {
- debug("Cannot get RAM size: %d\n", ret);
+ log_debug("Cannot get RAM size: %d\n", ret);
return ret;
}
- debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+ log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
gd->ram_size = ram.size;
diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c
index 0de1d82..aaedeac 100644
--- a/arch/arm/mach-stm32mp/fdt.c
+++ b/arch/arm/mach-stm32mp/fdt.c
@@ -3,6 +3,8 @@
* Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY LOGC_ARCH
+
#include <common.h>
#include <fdt_support.h>
#include <log.h>
@@ -172,15 +174,15 @@
status = (decprot[offset] >> shift) & DECPROT_MASK;
addr = array[i];
- debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
+ log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
if (addr == ETZPC_RESERVED ||
status == DECPROT_NON_SECURED)
continue;
if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
- printf("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
- addr, i, status);
+ log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
+ addr, i, status);
}
return 0;
@@ -194,7 +196,7 @@
off = fdt_path_offset(blob, "/cpus");
if (off < 0) {
- printf("%s: couldn't find /cpus node\n", __func__);
+ log_warning("%s: couldn't find /cpus node\n", __func__);
return;
}
@@ -203,7 +205,8 @@
reg = fdtdec_get_addr(blob, off, "reg");
if (reg != 0) {
fdt_del_node(blob, off);
- printf("FDT: cpu %d node remove for %s\n", reg, name);
+ log_notice("FDT: cpu %d node remove for %s\n",
+ reg, name);
/* after delete we can't trust the offsets anymore */
off = -1;
}
@@ -216,8 +219,8 @@
const char *string, const char *name)
{
if (fdt_disable_subnode_by_address(fdt, offset, addr))
- printf("FDT: %s@%08x node disabled for %s\n",
- string, addr, name);
+ log_notice("FDT: %s@%08x node disabled for %s\n",
+ string, addr, name);
}
static void stm32_fdt_disable_optee(void *blob)
diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/pwr_regulator.c
index 766ed95..846637a 100644
--- a/arch/arm/mach-stm32mp/pwr_regulator.c
+++ b/arch/arm/mach-stm32mp/pwr_regulator.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_REGULATOR
+
#include <common.h>
#include <dm.h>
#include <errno.h>
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index 66a6346..0c50ad5 100644
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY LOGC_ARCH
+
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
@@ -80,7 +82,7 @@
*/
model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
if (model)
- printf("Model: %s\n", model);
+ log_info("Model: %s\n", model);
}
#endif
@@ -98,25 +100,25 @@
ret = spl_early_init();
if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
+ log_debug("spl_early_init() failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
- debug("Clock init failed: %d\n", ret);
+ log_debug("Clock init failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_RESET, 0, &dev);
if (ret) {
- debug("Reset init failed: %d\n", ret);
+ log_debug("Reset init failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
+ log_debug("%s: Cannot find pinctrl device\n", __func__);
hang();
}
@@ -125,13 +127,13 @@
ret = board_early_init_f();
if (ret) {
- debug("board_early_init_f() failed: %d\n", ret);
+ log_debug("board_early_init_f() failed: %d\n", ret);
hang();
}
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- printf("DRAM init failed: %d\n", ret);
+ log_err("DRAM init failed: %d\n", ret);
hang();
}
diff --git a/board/amlogic/beelink-s922x/MAINTAINERS b/board/amlogic/beelink-s922x/MAINTAINERS
new file mode 100644
index 0000000..7f223df
--- /dev/null
+++ b/board/amlogic/beelink-s922x/MAINTAINERS
@@ -0,0 +1,9 @@
+BEELINK-S922X
+M: Christian Hewitt <christianshewitt@gmail.com>
+S: Maintained
+L: u-boot-amlogic@groups.io
+F: board/amlogic/beelink-s922x/
+F: configs/beelink-gtking_defconfig
+F: configs/beelink-gtkingpro_defconfig
+F: doc/board/amlogic/beelink-gtking.rst
+F: doc/board/amlogic/beelink-gtkingpro.rst
diff --git a/board/amlogic/beelink-s922x/Makefile b/board/amlogic/beelink-s922x/Makefile
new file mode 100644
index 0000000..27b1a74
--- /dev/null
+++ b/board/amlogic/beelink-s922x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 BayLibre, SAS
+# Author: Neil Armstrong <narmstrong@baylibre.com>
+
+obj-y := beelink-s922x.o
diff --git a/board/amlogic/beelink-s922x/beelink-s922x.c b/board/amlogic/beelink-s922x/beelink-s922x.c
new file mode 100644
index 0000000..dc0d933
--- /dev/null
+++ b/board/amlogic/beelink-s922x/beelink-s922x.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/sm.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/boot.h>
+
+#define EFUSE_MAC_OFFSET 20
+#define EFUSE_MAC_SIZE 12
+#define MAC_ADDR_LEN 6
+
+int misc_init_r(void)
+{
+ u8 mac_addr[MAC_ADDR_LEN];
+ char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
+ ssize_t len;
+
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) &&
+ meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
+ env_set("soc_rev", tmp);
+
+ meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ efuse_mac_addr, EFUSE_MAC_SIZE);
+ if (len != EFUSE_MAC_SIZE)
+ return 0;
+
+ /* MAC is stored in ASCII format, 1bytes = 2characters */
+ for (int i = 0; i < 6; i++) {
+ tmp[0] = efuse_mac_addr[i * 2];
+ tmp[1] = efuse_mac_addr[i * 2 + 1];
+ tmp[2] = '\0';
+ mac_addr[i] = simple_strtoul(tmp, NULL, 16);
+ }
+
+ if (is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ else
+ meson_generate_serial_ethaddr();
+ }
+
+ return 0;
+}
diff --git a/board/amlogic/odroid-n2/odroid-n2.c b/board/amlogic/odroid-n2/odroid-n2.c
index caf7fd6..d995543 100644
--- a/board/amlogic/odroid-n2/odroid-n2.c
+++ b/board/amlogic/odroid-n2/odroid-n2.c
@@ -10,19 +10,32 @@
#include <init.h>
#include <net.h>
#include <asm/io.h>
+#include <asm/arch/boot.h>
#include <asm/arch/sm.h>
#include <asm/arch/eth.h>
+#include <asm/arch/boot.h>
#define EFUSE_MAC_OFFSET 20
#define EFUSE_MAC_SIZE 12
#define MAC_ADDR_LEN 6
+int mmc_get_env_dev(void)
+{
+ if (meson_get_boot_device() == BOOT_DEVICE_EMMC)
+ return 1;
+ return 0;
+}
+
int misc_init_r(void)
{
u8 mac_addr[MAC_ADDR_LEN];
char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
ssize_t len;
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) &&
+ meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
+ env_set("soc_rev", tmp);
+
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS
index cae6994..3d622af 100644
--- a/board/amlogic/p212/MAINTAINERS
+++ b/board/amlogic/p212/MAINTAINERS
@@ -7,6 +7,7 @@
F: configs/khadas-vim_defconfig
F: configs/libretech-ac_defconfig
F: configs/libretech-cc_defconfig
+F: configs/libretech-cc_v2_defconfig
F: configs/p212_defconfig
F: doc/board/amlogic/p212.rst
F: doc/board/amlogic/libretech-ac.rst
diff --git a/board/amlogic/q200/MAINTAINERS b/board/amlogic/q200/MAINTAINERS
index ec05aa6..ba7c12b 100644
--- a/board/amlogic/q200/MAINTAINERS
+++ b/board/amlogic/q200/MAINTAINERS
@@ -7,4 +7,6 @@
F: configs/khadas-vim2_defconfig
F: configs/libretech-s905d-pc_defconfig
F: configs/libretech-s912-pc_defconfig
+F: configs/wetek-core2_defconfig
F: doc/board/amlogic/khadas-vim2.rst
+F: doc/board/amlogic/wetek-core2.rst
diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c
index 09ef39f..7145dbe 100644
--- a/board/amlogic/vim3/vim3.c
+++ b/board/amlogic/vim3/vim3.c
@@ -10,10 +10,19 @@
#include <init.h>
#include <net.h>
#include <asm/io.h>
+#include <asm/arch/boot.h>
#include <asm/arch/eth.h>
+#include <asm/arch/sm.h>
#include <i2c.h>
#include "khadas-mcu.h"
+int mmc_get_env_dev(void)
+{
+ if (meson_get_boot_device() == BOOT_DEVICE_EMMC)
+ return 2;
+ return 1;
+}
+
/*
* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
@@ -129,9 +138,39 @@
return 0;
}
+#define EFUSE_MAC_OFFSET 0
+#define EFUSE_MAC_SIZE 12
+#define MAC_ADDR_LEN 6
+
int misc_init_r(void)
{
+ u8 mac_addr[MAC_ADDR_LEN];
+ char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
+ ssize_t len;
+
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+ efuse_mac_addr, EFUSE_MAC_SIZE);
+ if (len != EFUSE_MAC_SIZE)
+ return 0;
+
+ /* MAC is stored in ASCII format, 1bytes = 2characters */
+ for (int i = 0; i < 6; i++) {
+ tmp[0] = efuse_mac_addr[i * 2];
+ tmp[1] = efuse_mac_addr[i * 2 + 1];
+ tmp[2] = '\0';
+ mac_addr[i] = simple_strtoul(tmp, NULL, 16);
+ }
+
+ if (is_valid_ethaddr(mac_addr))
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ else
+ meson_generate_serial_ethaddr();
+
+ eth_env_get_enetaddr("ethaddr", mac_addr);
+ }
+
return 0;
}
diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
index ba48786..8eed9d0 100644
--- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
+++ b/board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its
@@ -47,28 +47,28 @@
config-1 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-pdk2_somrev0_boardrev0";
- loadables = "uboot";
+ firmware = "uboot";
fdt = "fdt-1";
};
config-2 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-pdk2_somrev1_boardrev0";
- loadables = "uboot";
+ firmware = "uboot";
fdt = "fdt-1";
};
config-3 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-drc02_somrev0_boardrev0";
- loadables = "uboot";
+ firmware = "uboot";
fdt = "fdt-2";
};
config-4 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcom-drc02_somrev1_boardrev0";
- loadables = "uboot";
+ firmware = "uboot";
fdt = "fdt-2";
};
diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
index 7419684..0ea10a1 100644
--- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
+++ b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
@@ -31,7 +31,7 @@
config-1 {
/* DT+SoM+board model */
description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1";
- loadables = "uboot";
+ firmware = "uboot";
fdt = "fdt-1";
};
diff --git a/board/st/common/MAINTAINERS b/board/st/common/MAINTAINERS
index 3b02f4a..c4e0c5f 100644
--- a/board/st/common/MAINTAINERS
+++ b/board/st/common/MAINTAINERS
@@ -1,5 +1,5 @@
ST BOARDS
-M: Patrick Delaunay <patrick.delaunay@st.com>
+M: Patrick Delaunay <patrick.delaunay@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c
index 9c3d115..5633a6c 100644
--- a/board/st/common/stm32mp_dfu.c
+++ b/board/st/common/stm32mp_dfu.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <dfu.h>
#include <env.h>
+#include <log.h>
#include <memalign.h>
#include <misc.h>
#include <mtd.h>
@@ -199,7 +200,7 @@
ret = 0;
}
#else
- pr_err("PMIC update not supported");
+ log_err("PMIC update not supported");
ret = -EOPNOTSUPP;
#endif
diff --git a/board/st/common/stm32mp_mtdparts.c b/board/st/common/stm32mp_mtdparts.c
index 9f5897f..71a0b44 100644
--- a/board/st/common/stm32mp_mtdparts.c
+++ b/board/st/common/stm32mp_mtdparts.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <env.h>
#include <env_internal.h>
+#include <log.h>
#include <mtd.h>
#include <mtd_node.h>
#include <tee.h>
@@ -117,7 +118,7 @@
for (uclass_first_device(UCLASS_MTD, &dev);
dev;
uclass_next_device(&dev)) {
- pr_debug("mtd device = %s\n", dev->name);
+ log_debug("mtd device = %s\n", dev->name);
}
if (nor || nand) {
@@ -163,5 +164,5 @@
mtd_initialized = true;
*mtdids = ids;
*mtdparts = parts;
- debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts);
+ log_debug("mtdids=%s & mtdparts=%s\n", ids, parts);
}
diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c
index a313b81..5fb1be2 100644
--- a/board/st/common/stpmic1.c
+++ b/board/st/common/stpmic1.c
@@ -3,8 +3,11 @@
* Copyright (C) 2020, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY LOGC_BOARD
+
#include <common.h>
#include <dm.h>
+#include <log.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <linux/bitops.h>
@@ -202,7 +205,7 @@
/* Check if debug is enabled to program PMIC according to the bit */
if (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_DEBUG_ON) {
- printf("Keep debug unit ON\n");
+ log_info("Keep debug unit ON\n");
pmic_clrsetbits(dev, STPMIC1_BUCKS_MRST_CR,
STPMIC1_MRST_BUCK_DEBUG,
diff --git a/board/st/common/stusb160x.c b/board/st/common/stusb160x.c
index e0a2b76..f0385e5 100644
--- a/board/st/common/stusb160x.c
+++ b/board/st/common/stusb160x.c
@@ -6,6 +6,8 @@
* Copyright (C) 2020, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_I2C_GENERIC
+
#include <common.h>
#include <dm.h>
#include <i2c.h>
diff --git a/board/st/stih410-b2260/MAINTAINERS b/board/st/stih410-b2260/MAINTAINERS
index 4f557ac..6fa6255 100644
--- a/board/st/stih410-b2260/MAINTAINERS
+++ b/board/st/stih410-b2260/MAINTAINERS
@@ -1,5 +1,5 @@
STIH410-B2260 BOARD
-M: Patrice Chotard <patrice.chotard@st.com>
+M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stih410-b2260/
F: include/configs/stih410-b2260.h
diff --git a/board/st/stih410-b2260/Makefile b/board/st/stih410-b2260/Makefile
index dc3e1d3..ea573ca 100644
--- a/board/st/stih410-b2260/Makefile
+++ b/board/st/stih410-b2260/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
-# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y = board.o
diff --git a/board/st/stm32f429-evaluation/MAINTAINERS b/board/st/stm32f429-evaluation/MAINTAINERS
index 8b7b312..29d00ef 100644
--- a/board/st/stm32f429-evaluation/MAINTAINERS
+++ b/board/st/stm32f429-evaluation/MAINTAINERS
@@ -1,5 +1,5 @@
STM32F429-EVALUATION BOARD
-M: Patrice Chotard <patrice.chotard@st.com>
+M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stm32f429-evaluation/
F: include/configs/stm32f429-evaluation.h
diff --git a/board/st/stm32f429-evaluation/Makefile b/board/st/stm32f429-evaluation/Makefile
index 8bf9e1f..109fba8 100644
--- a/board/st/stm32f429-evaluation/Makefile
+++ b/board/st/stm32f429-evaluation/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
-# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y := stm32f429-evaluation.o
diff --git a/board/st/stm32f469-discovery/MAINTAINERS b/board/st/stm32f469-discovery/MAINTAINERS
index d3c791a..5a6a78b 100644
--- a/board/st/stm32f469-discovery/MAINTAINERS
+++ b/board/st/stm32f469-discovery/MAINTAINERS
@@ -1,5 +1,5 @@
STM32F469-DISCOVERY BOARD
-M: Patrice Chotard <patrice.chotard@st.com>
+M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stm32f469-discovery/
F: include/configs/stm32f469-discovery.h
diff --git a/board/st/stm32f469-discovery/Makefile b/board/st/stm32f469-discovery/Makefile
index 249835b..45480b7 100644
--- a/board/st/stm32f469-discovery/Makefile
+++ b/board/st/stm32f469-discovery/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) STMicroelectronics SA 2017
-# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y := stm32f469-discovery.o
diff --git a/board/st/stm32h743-disco/MAINTAINERS b/board/st/stm32h743-disco/MAINTAINERS
index e5e0b5a..60fbe34 100644
--- a/board/st/stm32h743-disco/MAINTAINERS
+++ b/board/st/stm32h743-disco/MAINTAINERS
@@ -1,5 +1,5 @@
STM32H743 DISCOVERY BOARD
-M: Patrice Chotard <patrice.chotard@st.com>
+M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stm32h743-disco
F: include/configs/stm32h743-disco.h
diff --git a/board/st/stm32h743-disco/Makefile b/board/st/stm32h743-disco/Makefile
index 8fe7a2d..b6c22be 100644
--- a/board/st/stm32h743-disco/Makefile
+++ b/board/st/stm32h743-disco/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
-# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y := stm32h743-disco.o
diff --git a/board/st/stm32h743-eval/MAINTAINERS b/board/st/stm32h743-eval/MAINTAINERS
index 3029c560..fda93db 100644
--- a/board/st/stm32h743-eval/MAINTAINERS
+++ b/board/st/stm32h743-eval/MAINTAINERS
@@ -1,5 +1,5 @@
STM32H743 EVALUATION BOARD
-M: Patrice Chotard <patrice.chotard@st.com>
+M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
F: board/st/stm32h743-eval
F: include/configs/stm32h743-eval.h
diff --git a/board/st/stm32h743-eval/Makefile b/board/st/stm32h743-eval/Makefile
index 88b59fd..86ef19f 100644
--- a/board/st/stm32h743-eval/Makefile
+++ b/board/st/stm32h743-eval/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
-# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+# Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
obj-y := stm32h743-eval.o
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
index 96c4559..bd5c07d 100644
--- a/board/st/stm32mp1/MAINTAINERS
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -1,5 +1,5 @@
STM32MP1 BOARD
-M: Patrick Delaunay <patrick.delaunay@st.com>
+M: Patrick Delaunay <patrick.delaunay@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index df353cb..78362d2 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+
+#define LOG_CATEGORY LOGC_BOARD
+
#include <common.h>
#include <adc.h>
#include <bootm.h>
@@ -106,12 +109,11 @@
else
mode = "basic";
- printf("Board: stm32mp1 in %s mode", mode);
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
&fdt_compat_len);
- if (fdt_compat && fdt_compat_len)
- printf(" (%s)", fdt_compat);
- puts("\n");
+
+ log_info("Board: stm32mp1 in %s mode (%s)\n", mode,
+ fdt_compat && fdt_compat_len ? fdt_compat : "");
/* display the STMicroelectronics board identification */
if (CONFIG_IS_ENABLED(CMD_STBOARD)) {
@@ -122,12 +124,12 @@
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
&otp, sizeof(otp));
if (ret > 0 && otp)
- printf("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
- otp >> 16,
- (otp >> 12) & 0xF,
- (otp >> 4) & 0xF,
- ((otp >> 8) & 0xF) - 1 + 'A',
- otp & 0xF);
+ log_info("Board: MB%04x Var%d.%d Rev.%c-%02d\n",
+ otp >> 16,
+ (otp >> 12) & 0xF,
+ (otp >> 4) & 0xF,
+ ((otp >> 8) & 0xF) - 1 + 'A',
+ otp & 0xF);
}
return 0;
@@ -144,17 +146,16 @@
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
- debug("%s: no /config node?\n", __func__);
+ log_debug("no /config node?\n");
return;
}
if (IS_ENABLED(CONFIG_FASTBOOT)) {
if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
&gpio, GPIOD_IS_IN)) {
- debug("%s: could not find a /config/st,fastboot-gpios\n",
- __func__);
+ log_debug("could not find a /config/st,fastboot-gpios\n");
} else {
if (dm_gpio_get_value(&gpio)) {
- puts("Fastboot key pressed, ");
+ log_notice("Fastboot key pressed, ");
boot_mode = BOOT_FASTBOOT;
}
@@ -164,18 +165,17 @@
if (IS_ENABLED(CONFIG_CMD_STM32PROG)) {
if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
&gpio, GPIOD_IS_IN)) {
- debug("%s: could not find a /config/st,stm32prog-gpios\n",
- __func__);
+ log_debug("could not find a /config/st,stm32prog-gpios\n");
} else {
if (dm_gpio_get_value(&gpio)) {
- puts("STM32Programmer key pressed, ");
+ log_notice("STM32Programmer key pressed, ");
boot_mode = BOOT_STM32PROG;
}
dm_gpio_free(NULL, &gpio);
}
}
if (boot_mode != BOOT_NORMAL) {
- puts("entering download mode...\n");
+ log_notice("entering download mode...\n");
clrsetbits_le32(TAMP_BOOT_CONTEXT,
TAMP_BOOT_FORCED_MASK,
boot_mode);
@@ -198,8 +198,10 @@
ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
DM_DRIVER_GET(dwc2_udc_otg),
&dwc2_udc_otg);
- if (!ret)
- debug("dwc2_udc_otg init failed\n");
+ if (ret) {
+ log_debug("dwc2_udc_otg init failed\n");
+ return ret;
+ }
return dwc2_udc_B_session_valid(dwc2_udc_otg);
}
@@ -231,13 +233,12 @@
led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
if (!led_name) {
- pr_debug("%s: could not find %s config string\n",
- __func__, led_string);
+ log_debug("could not find %s config string\n", led_string);
return -ENOENT;
}
ret = led_get_by_label(led_name, dev);
if (ret) {
- debug("%s: get=%d\n", __func__, ret);
+ log_debug("get=%d\n", ret);
return ret;
}
@@ -288,24 +289,66 @@
hang();
}
-static int board_check_usb_power(void)
+static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV)
{
struct ofnode_phandle_args adc_args;
struct udevice *adc;
- ofnode node;
unsigned int raw;
+ int ret, uV;
+ int i;
+
+ for (i = 0; i < adc_count; i++) {
+ if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
+ "#io-channel-cells", 0, i,
+ &adc_args)) {
+ log_debug("can't find /config/st,adc_usb_pd\n");
+ return 0;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
+ &adc);
+
+ if (ret) {
+ log_err("Can't get adc device(%d)\n", ret);
+ return ret;
+ }
+
+ ret = adc_channel_single_shot(adc->name, adc_args.args[0],
+ &raw);
+ if (ret) {
+ log_err("single shot failed for %s[%d]!\n",
+ adc->name, adc_args.args[0]);
+ return ret;
+ }
+ /* Convert to uV */
+ if (!adc_raw_to_uV(adc, raw, &uV)) {
+ if (uV > *max_uV)
+ *max_uV = uV;
+ if (uV < *min_uV)
+ *min_uV = uV;
+ log_debug("%s[%02d] = %u, %d uV\n",
+ adc->name, adc_args.args[0], raw, uV);
+ } else {
+ log_err("Can't get uV value for %s[%d]\n",
+ adc->name, adc_args.args[0]);
+ }
+ }
+
+ return 0;
+}
+
+static int board_check_usb_power(void)
+{
+ ofnode node;
int max_uV = 0;
int min_uV = USB_START_HIGH_THRESHOLD_UV;
- int ret, uV, adc_count;
+ int adc_count, ret;
u32 nb_blink;
u8 i;
- if (!IS_ENABLED(CONFIG_ADC))
- return -ENODEV;
-
node = ofnode_path("/config");
if (!ofnode_valid(node)) {
- debug("%s: no /config node?\n", __func__);
+ log_debug("no /config node?\n");
return -ENOENT;
}
@@ -319,63 +362,38 @@
if (adc_count == -ENOENT)
return 0;
- pr_err("%s: can't find adc channel (%d)\n", __func__,
- adc_count);
+ log_err("Can't find adc channel (%d)\n", adc_count);
return adc_count;
}
- for (i = 0; i < adc_count; i++) {
- if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
- "#io-channel-cells", 0, i,
- &adc_args)) {
- pr_debug("%s: can't find /config/st,adc_usb_pd\n",
- __func__);
+ /* perform maximum of 2 ADC measurements to detect power supply current */
+ for (i = 0; i < 2; i++) {
+ if (IS_ENABLED(CONFIG_ADC))
+ ret = adc_measurement(node, adc_count, &min_uV, &max_uV);
+ else
+ ret = -ENODEV;
+
+ if (ret)
+ return ret;
+
+ /*
+ * If highest value is inside 1.23 Volts and 2.10 Volts, that means
+ * board is plugged on an USB-C 3A power supply and boot process can
+ * continue.
+ */
+ if (max_uV > USB_START_LOW_THRESHOLD_UV &&
+ max_uV <= USB_START_HIGH_THRESHOLD_UV &&
+ min_uV <= USB_LOW_THRESHOLD_UV)
return 0;
- }
- ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
- &adc);
-
- if (ret) {
- pr_err("%s: Can't get adc device(%d)\n", __func__,
- ret);
- return ret;
- }
-
- ret = adc_channel_single_shot(adc->name, adc_args.args[0],
- &raw);
- if (ret) {
- pr_err("%s: single shot failed for %s[%d]!\n",
- __func__, adc->name, adc_args.args[0]);
- return ret;
- }
- /* Convert to uV */
- if (!adc_raw_to_uV(adc, raw, &uV)) {
- if (uV > max_uV)
- max_uV = uV;
- if (uV < min_uV)
- min_uV = uV;
- pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__,
- adc->name, adc_args.args[0], raw, uV);
- } else {
- pr_err("%s: Can't get uV value for %s[%d]\n",
- __func__, adc->name, adc_args.args[0]);
+ if (i == 0) {
+ log_err("Previous ADC measurements was not the one expected, retry in 20ms\n");
+ mdelay(20); /* equal to max tPDDebounce duration (min 10ms - max 20ms) */
}
}
- /*
- * If highest value is inside 1.23 Volts and 2.10 Volts, that means
- * board is plugged on an USB-C 3A power supply and boot process can
- * continue.
- */
- if (max_uV > USB_START_LOW_THRESHOLD_UV &&
- max_uV <= USB_START_HIGH_THRESHOLD_UV &&
- min_uV <= USB_LOW_THRESHOLD_UV)
- return 0;
-
- pr_err("****************************************************\n");
-
+ log_notice("****************************************************\n");
/*
* If highest and lowest value are either both below
* USB_LOW_THRESHOLD_UV or both above USB_LOW_THRESHOLD_UV, that
@@ -386,8 +404,8 @@
min_uV > USB_LOW_THRESHOLD_UV) ||
(max_uV <= USB_LOW_THRESHOLD_UV &&
min_uV <= USB_LOW_THRESHOLD_UV)) {
- pr_err("* ERROR USB TYPE-C connection in unattached mode *\n");
- pr_err("* Check that USB TYPE-C cable is correctly plugged *\n");
+ log_notice("* ERROR USB TYPE-C connection in unattached mode *\n");
+ log_notice("* Check that USB TYPE-C cable is correctly plugged *\n");
/* with 125ms interval, led will blink for 17.02 years ....*/
nb_blink = U32_MAX;
}
@@ -395,14 +413,14 @@
if (max_uV > USB_LOW_THRESHOLD_UV &&
max_uV <= USB_WARNING_LOW_THRESHOLD_UV &&
min_uV <= USB_LOW_THRESHOLD_UV) {
- pr_err("* WARNING 500mA power supply detected *\n");
+ log_notice("* WARNING 500mA power supply detected *\n");
nb_blink = 2;
}
if (max_uV > USB_WARNING_LOW_THRESHOLD_UV &&
max_uV <= USB_START_LOW_THRESHOLD_UV &&
min_uV <= USB_LOW_THRESHOLD_UV) {
- pr_err("* WARNING 1.5A power supply detected *\n");
+ log_notice("* WARNING 1.5A power supply detected *\n");
nb_blink = 3;
}
@@ -411,14 +429,14 @@
* supplies more than 3 Amp, this is not compliant with TypeC specification
*/
if (max_uV > USB_START_HIGH_THRESHOLD_UV) {
- pr_err("* USB TYPE-C charger not compliant with *\n");
- pr_err("* specification *\n");
- pr_err("****************************************************\n\n");
+ log_notice("* USB TYPE-C charger not compliant with *\n");
+ log_notice("* specification *\n");
+ log_notice("****************************************************\n\n");
/* with 125ms interval, led will blink for 17.02 years ....*/
nb_blink = U32_MAX;
} else {
- pr_err("* Current too low, use a 3A power supply! *\n");
- pr_err("****************************************************\n\n");
+ log_notice("* Current too low, use a 3A power supply! *\n");
+ log_notice("****************************************************\n\n");
}
led_error_blink(nb_blink);
@@ -471,7 +489,7 @@
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret) {
- pr_err("Can't find stm32mp_bsec driver\n");
+ log_err("Can't find stm32mp_bsec driver\n");
return;
}
@@ -494,13 +512,13 @@
syscfg + SYSCFG_IOCTRLSETR);
if (!otp)
- pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
+ log_err("product_below_2v5=0: HSLVEN protected by HW\n");
} else {
if (otp)
- pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
+ log_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
}
} else {
- debug("VDD unknown");
+ log_debug("VDD unknown");
}
}
@@ -514,7 +532,7 @@
val & SYSCFG_CMPCR_READY,
1000000);
if (ret) {
- pr_err("SYSCFG: I/O compensation failed, timeout.\n");
+ log_err("SYSCFG: I/O compensation failed, timeout.\n");
led_error_blink(10);
}
@@ -533,39 +551,37 @@
node = ofnode_path("/soc/i2c@40012000/hdmi-transmitter@39");
if (!ofnode_valid(node)) {
- pr_debug("%s: no hdmi-transmitter@39 ?\n", __func__);
+ log_debug("no hdmi-transmitter@39 ?\n");
return -ENOENT;
}
if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
&hdmi, GPIOD_IS_OUT)) {
- pr_debug("%s: could not find reset-gpios\n",
- __func__);
+ log_debug("could not find reset-gpios\n");
return -ENOENT;
}
node = ofnode_path("/soc/i2c@40012000/cs42l51@4a");
if (!ofnode_valid(node)) {
- pr_debug("%s: no cs42l51@4a ?\n", __func__);
+ log_debug("no cs42l51@4a ?\n");
return -ENOENT;
}
if (gpio_request_by_name_nodev(node, "reset-gpios", 0,
&audio, GPIOD_IS_OUT)) {
- pr_debug("%s: could not find reset-gpios\n",
- __func__);
+ log_debug("could not find reset-gpios\n");
return -ENOENT;
}
/* before power up, insure that HDMI and AUDIO IC is under reset */
ret = dm_gpio_set_value(&hdmi, 1);
if (ret) {
- pr_err("%s: can't set_value for hdmi_nrst gpio", __func__);
+ log_err("can't set_value for hdmi_nrst gpio");
goto error;
}
ret = dm_gpio_set_value(&audio, 1);
if (ret) {
- pr_err("%s: can't set_value for audio_nrst gpio", __func__);
+ log_err("can't set_value for audio_nrst gpio");
goto error;
}
@@ -732,7 +748,7 @@
case PHY_INTERFACE_MODE_MII:
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
- debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
+ log_debug("PHY_INTERFACE_MODE_MII\n");
break;
case PHY_INTERFACE_MODE_GMII:
if (eth_clk_sel_reg)
@@ -740,7 +756,7 @@
SYSCFG_PMCSETR_ETH_CLK_SEL;
else
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
- debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
+ log_debug("PHY_INTERFACE_MODE_GMII\n");
break;
case PHY_INTERFACE_MODE_RMII:
if (eth_ref_clk_sel_reg)
@@ -748,7 +764,7 @@
SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
else
value = SYSCFG_PMCSETR_ETH_SEL_RMII;
- debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
+ log_debug("PHY_INTERFACE_MODE_RMII\n");
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
@@ -759,11 +775,11 @@
SYSCFG_PMCSETR_ETH_CLK_SEL;
else
value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
- debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
+ log_debug("PHY_INTERFACE_MODE_RGMII\n");
break;
default:
- debug("%s: Do not manage %d interface\n",
- __func__, interface_type);
+ log_debug("Do not manage %d interface\n",
+ interface_type);
/* Do not manage others interfaces */
return -EINVAL;
}
@@ -878,14 +894,14 @@
if (!rproc_is_initialized())
if (rproc_init()) {
- printf("Remote Processor %d initialization failed\n",
- id);
+ log_err("Remote Processor %d initialization failed\n",
+ id);
return;
}
ret = rproc_load(id, fw_image, fw_size);
- printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
- id, fw_image, fw_size, ret ? " Failed!" : " Success!");
+ log_err("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
+ id, fw_image, fw_size, ret ? " Failed!" : " Success!");
if (!ret)
rproc_start(id);
diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig
new file mode 100644
index 0000000..ea42887
--- /dev/null
+++ b/configs/beelink-gtking_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="beelink-s922x"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" beelink"
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking"
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig
new file mode 100644
index 0000000..5690316
--- /dev/null
+++ b/configs/beelink-gtkingpro_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SYS_BOARD="beelink-s922x"
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_MESON_G12A=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" beelink"
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking-pro"
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MESON_G12A_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index 9d7ba72..5d16652 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -29,6 +29,8 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_DM_MMC=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index f37993e..6b13ce0 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -29,6 +29,8 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_DM_MMC=y
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index 171d793..ca61591 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -51,7 +51,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index aaab1a2..fb4bf4c 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -38,7 +38,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig
new file mode 100644
index 0000000..e71f88e
--- /dev/null
+++ b/configs/libretech-cc_v2_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFF0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_MESON_GXL=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" libretech-cc-v2"
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc-v2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ADDR=8
+CONFIG_PHY_MESON_GXL=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MESON_SPIFC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index f4e289a..9d4c880 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -46,7 +46,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index 24e410c..cf600c1 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -45,7 +45,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 14e8405..5c02fa1 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -38,7 +38,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXBB=y
CONFIG_POWER_DOMAIN=y
-CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_MESON_EE_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 1843bbc..d3e5775 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -21,6 +21,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SPL_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
@@ -54,8 +55,10 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 964f4c2..d392b0f 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -38,7 +38,9 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
+CONFIG_OF_LIVE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig
new file mode 100644
index 0000000..706abff
--- /dev/null
+++ b/configs/wetek-core2_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_MESON_GXM=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_IDENT_STRING=" wetek-core2"
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-wetek-core2"
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SARADC_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MESON_GXL_USB_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MESON_GXL=y
+CONFIG_DM_REGULATOR=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_RESET=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP16 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MESON=y
+CONFIG_VIDEO_DT_SIMPLEFB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_MESON_GXL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/doc/board/amlogic/beelink-gtking.rst b/doc/board/amlogic/beelink-gtking.rst
new file mode 100644
index 0000000..56ce2cb
--- /dev/null
+++ b/doc/board/amlogic/beelink-gtking.rst
@@ -0,0 +1,115 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GT-King
+==========================
+
+The Shenzen AZW (Beelink) GT-King is based on the Amlogic W400 reference
+board with an S922X-H chip.
+
+- 4GB LPDDR4 RAM
+- 64GB eMMC storage
+- 10/100/1000 Base-T Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1)
+- HDMI 2.1 video
+- S/PDIF optical output
+- Analogue audio output
+- 1x USB 2.0 port
+- 2x USB 3.0 ports
+- IR receiver
+- 1x micro SD card slot
+
+Beelink do not provide public schematics, but have been willing
+to share them with known distro developers on request.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make beelink-gtking_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic does not provide sources for the firmware and for tools needed
+to create the bootloader image. Beelink have provided the Amlogic "SDK"
+in their forums, but the u-boot sources included result in 2GB RAM being
+detected. The following FIPs were generated with newer private sources
+and give correct (4GB) RAM detection:
+
+https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+
+NB: Beelink use a common board config for GT-King, GT-King Pro and the
+GS-King-X model, hence the "beelink-s922x" name.
+
+.. code-block:: bash
+
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
+ $ unzip master.zip
+ $ export FIPDIR=$PWD/amlogic-boot-fip/beelink-s922x
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+ $ cp $FIPDIR/* fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ fip/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_sd_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/doc/board/amlogic/beelink-gtkingpro.rst b/doc/board/amlogic/beelink-gtkingpro.rst
new file mode 100644
index 0000000..d750351
--- /dev/null
+++ b/doc/board/amlogic/beelink-gtkingpro.rst
@@ -0,0 +1,116 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for Beelink GT-King Pro
+==============================
+
+The Shenzen AZW (Beelink) GT-King Pro is based on the Amlogic W400 reference
+board with an S922X-H chip.
+
+- 4GB LPDDR4 RAM
+- 64GB eMMC storage
+- 10/100/1000 Base-T Ethernet
+- AP6356S Wireless (802.11 a/b/g/n/ac, BT 4.1)
+- HDMI 2.1 video
+- Analogue audio output
+- 1x RS232 port
+- 2x USB 2.0 port
+- 2x USB 3.0 ports
+- IR receiver
+- 1x SD card slot
+- 1x Power on/off button
+
+Beelink do not provide public schematics, but have been willing
+to share them with known distro developers on request.
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make beelink-gtkingpro_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic does not provide sources for the firmware and for tools needed
+to create the bootloader image. Beelink have provided the Amlogic "SDK"
+in their forums, but the u-boot sources included result in 2GB RAM being
+detected. The following FIPs were generated with newer private sources
+and give correct (4GB) RAM detection:
+
+https://github.com/LibreELEC/amlogic-boot-fip/tree/master/beelink-s922x
+
+NB: Beelink use a common board config for GT-King, GT-King Pro and the
+GS-King-X model, hence the "beelink-s922x" name.
+
+.. code-block:: bash
+
+ $ wget https://github.com/LibreELEC/amlogic-boot-fip/archive/master.zip
+ $ unzip master.zip
+ $ export FIPDIR=$PWD/amlogic-boot-fip/beelink-s922x
+
+Go back to the mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+ $ cp $FIPDIR/* fip/
+ $ cp u-boot.bin fip/bl33.bin
+
+ $ sh fip/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+
+ $ sh fip/blx_fix.sh \
+ fip/bl2.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/acs.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+
+ $ fip/aml_encrypt_g12b --bl30sig --input fip/bl30_new.bin \
+ --output fip/bl30_new.bin.g12a.enc \
+ --level v3
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl30_new.bin.g12a.enc \
+ --output fip/bl30_new.bin.enc \
+ --level v3 --type bl30
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl31.img \
+ --output fip/bl31.img.enc \
+ --level v3 --type bl31
+ $ fip/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
+ --output fip/bl33.bin.enc \
+ --level v3 --type bl33
+ $ fip/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
+ --output fip/bl2.n.bin.sig
+ $ fip/aml_encrypt_g12b --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc \
+ --ddrfw1 fip/ddr4_1d.fw \
+ --ddrfw2 fip/ddr4_2d.fw \
+ --ddrfw3 fip/ddr3_1d.fw \
+ --ddrfw4 fip/piei.fw \
+ --ddrfw5 fip/lpddr4_1d.fw \
+ --ddrfw6 fip/lpddr4_2d.fw \
+ --ddrfw7 fip/diag_lpddr4.fw \
+ --ddrfw8 fip/aml_ddr.fw \
+ --level v3
+
+and then write the image to SD with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_sd_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst
index 9e780ba..275c366 100644
--- a/doc/board/amlogic/index.rst
+++ b/doc/board/amlogic/index.rst
@@ -10,66 +10,66 @@
This matrix concerns the actual source code version.
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 |
-| | | S805X | S905D | | S905D2 | A311D | S905D3 |
-| | | | | | S905Y2 | | |
-+===============================+===========+==============+==============+============+============+=============+==============+
-| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 |
-| | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
-| | P200 | LibreTech-CC | | | | | Odroid-C4 |
-| | P201 | LibreTech-AC | | | | | |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| Infrared Decoder | No | No | No | No | No | No | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| SPI (CC) | No | No | No | No | No | No | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| NAND | No | No | No | No | No | No | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| CEC | No | No | No | *N/A* | No | No | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| Thermal Sensor | No | No | No | No | No | No | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
-| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
-+-------------------------------+-----------+--------------+--------------+------------+------------+-------------+--------------+
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| | S905 | S905X | S912 | A113X | S905X2 | S922X | S905X3 |
+| | | S805X | S905D | | S905D2 | A311D | S905D3 |
+| | | | | | S905Y2 | | |
++===============================+===========+=================+==============+============+============+=============+==============+
+| Boards | Odroid-C2 | P212 | Khadas VIM2 | S400 | U200 | Odroid-N2 | SEI610 |
+| | Nanopi-K2 | Khadas-VIM | Libretech-PC | | SEI510 | Khadas-VIM3 | Khadas-VIM3L |
+| | P200 | LibreTech-CC v1 | WeTek Core2 | | | GT-King/Pro | Odroid-C4 |
+| | P201 | LibreTech-AC v2 | | | | | |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| UART | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Pinctrl/GPIO | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Clock Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| PWM | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Reset Control | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Infrared Decoder | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Ethernet | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Multi-core | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Fuse access | **Yes** | **Yes** |**Yes** |**Yes** |**Yes** |**Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| SPI (FC) | **Yes** | **Yes** | **Yes** | **Yes** |**Yes** | **Yes** | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| SPI (CC) | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| I2C | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| USB | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| USB OTG | No | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| eMMC | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| SDCard | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| NAND | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| ADC | **Yes** | **Yes** | **Yes** | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| CVBS Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| HDMI Output | **Yes** | **Yes** | **Yes** | *N/A* | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| CEC | No | No | No | *N/A* | No | No | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| Thermal Sensor | No | No | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| LCD/LVDS Output | No | *N/A* | No | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| MIPI DSI Output | *N/A* | *N/A* | *N/A* | No | No | No | No |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
+| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
++-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
Board Documentation
-------------------
@@ -77,6 +77,8 @@
.. toctree::
:maxdepth: 1
+ beelink-gtking
+ beelink-gtkingpro
khadas-vim2
khadas-vim3l
khadas-vim3
@@ -95,4 +97,5 @@
sei510
sei610
u200
+ wetek-core2
w400
diff --git a/doc/board/amlogic/libretech-cc.rst b/doc/board/amlogic/libretech-cc.rst
index f2e26ca..94c74c5 100644
--- a/doc/board/amlogic/libretech-cc.rst
+++ b/doc/board/amlogic/libretech-cc.rst
@@ -1,11 +1,13 @@
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for LibreTech CC
-=======================
+U-Boot for LibreTech CCs
+========================
LibreTech CC is a single board computer manufactured by Libre Technology
with the following specifications:
+V1:
+
- Amlogic S905X ARM Cortex-A53 quad-core SoC @ 1.5GHz
- ARM Mali 450 GPU
- 2GB DDR3 SDRAM
@@ -15,6 +17,12 @@
- 4 x USB 2.0 Host
- eMMC, microSD
- Infrared receiver
+ - Jack for CVBS and Audio
+
+V2:
+
+ - Added SPI NOR
+ - Removed Jack
Schematics are available on the manufacturer website.
@@ -27,6 +35,8 @@
$ make libretech-cc_defconfig
$ make
+Use libretech-cc_v2_defconfig for v2.
+
Image creation
--------------
@@ -41,7 +51,8 @@
* acs.bin: built from vendor u-boot source
These binaries and the tools required below have been collected and prebuilt
-for convenience at <https://github.com/BayLibre/u-boot/releases/>
+for convenience at <https://github.com/BayLibre/u-boot/releases/>. These
+apply to both v1 and v2.
Download and extract the libretech-cc release from there, and set FIPDIR to
point to the `fip` subdirectory.
diff --git a/doc/board/amlogic/wetek-core2.rst b/doc/board/amlogic/wetek-core2.rst
new file mode 100644
index 0000000..1012079
--- /dev/null
+++ b/doc/board/amlogic/wetek-core2.rst
@@ -0,0 +1,96 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for WeTek Core2
+======================
+
+WeTek Core2 is an Android STB based on the Q200 reference design with
+the following specifications:
+
+ - Amlogic S912 ARM Cortex-A53 octo-core SoC @ 1.5GHz
+ - ARM Mali T820 GPU
+ - 3GB DDR4 SDRAM
+ - 10/100 Realtek RTL8152 Ethernet (internal USB)
+ - HDMI 2.0 4K/60Hz display
+ - 2x USB 2.0 Host, 1x USB 2.0 OTG (internal)
+ - 32GB eMMC
+ - microSD
+ - SDIO Wifi Module, Bluetooth
+ - Two channel IR receiver
+
+U-Boot compilation
+------------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-none-elf-
+ $ make wetek-core2_defconfig
+ $ make
+
+Image creation
+--------------
+
+Amlogic does not provide sources for the firmware or the tools needed
+to create the bootloader image, and WeTek has not publicly shared the
+precompiled FIP binaries. However the public Khadas VIM2 sources also
+work with the Core2 box so we can use the Khadas git tree:
+
+.. code-block:: bash
+
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz
+ $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
+ $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
+ $ git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot
+ $ cd vim-u-boot
+ $ make kvim2_defconfig
+ $ make
+ $ export FIPDIR=$PWD/fip
+
+Go back to mainline U-Boot source tree then:
+
+.. code-block:: bash
+
+ $ mkdir fip
+ $ cp $FIPDIR/gxl/bl2.bin fip/
+ $ cp $FIPDIR/gxl/acs.bin fip/
+ $ cp $FIPDIR/gxl/bl21.bin fip/
+ $ cp $FIPDIR/gxl/bl30.bin fip/
+ $ cp $FIPDIR/gxl/bl301.bin fip/
+ $ cp $FIPDIR/gxl/bl31.img fip/
+ $ cp u-boot.bin fip/bl33.bin
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl30.bin \
+ fip/zero_tmp \
+ fip/bl30_zero.bin \
+ fip/bl301.bin \
+ fip/bl301_zero.bin \
+ fip/bl30_new.bin \
+ bl30
+ $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0
+ $ $FIPDIR/blx_fix.sh \
+ fip/bl2_acs.bin \
+ fip/zero_tmp \
+ fip/bl2_zero.bin \
+ fip/bl21.bin \
+ fip/bl21_zero.bin \
+ fip/bl2_new.bin \
+ bl2
+ $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin
+ $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img
+ $ $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin
+ $ $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig
+ $ $FIPDIR/gxl/aml_encrypt_gxl --bootmk \
+ --output fip/u-boot.bin \
+ --bl2 fip/bl2.n.bin.sig \
+ --bl30 fip/bl30_new.bin.enc \
+ --bl31 fip/bl31.img.enc \
+ --bl33 fip/bl33.bin.enc
+
+then write the image to SD with:
+
+.. code-block:: bash
+
+ $ DEV=/dev/your_sd_device
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1
+ $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444
diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
index e74f7af..20f5c9e 100644
--- a/doc/board/st/stm32mp1.rst
+++ b/doc/board/st/stm32mp1.rst
@@ -1,5 +1,5 @@
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-.. sectionauthor:: Patrick Delaunay <patrick.delaunay@st.com>
+.. sectionauthor:: Patrick Delaunay <patrick.delaunay@foss.st.com>
STM32MP15x boards
=================
diff --git a/doc/driver-model/bind.rst b/doc/driver-model/bind.rst
index e3e9cb4..b19661b 100644
--- a/doc/driver-model/bind.rst
+++ b/doc/driver-model/bind.rst
@@ -1,5 +1,5 @@
.. SPDX-License-Identifier: GPL-2.0+
-.. sectionauthor:: Patrice Chotard <patrice.chotard@st.com>
+.. sectionauthor:: Patrice Chotard <patrice.chotard@foss.st.com>
Binding/unbinding a driver
==========================
diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c
index 13a8f49..21db558 100644
--- a/drivers/adc/meson-saradc.c
+++ b/drivers/adc/meson-saradc.c
@@ -282,7 +282,7 @@
regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val);
fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
if (fifo_chan != channel) {
- printf("ADC FIFO entry belongs to channel %d instead of %d\n",
+ printf("ADC FIFO entry belongs to channel %u instead of %u\n",
fifo_chan, channel);
return -EINVAL;
}
@@ -512,8 +512,11 @@
* reading the temperature sensor.
*/
regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
- if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
- return 0;
+ if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) {
+ regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val);
+ if (regval & MESON_SAR_ADC_REG3_ADC_EN)
+ return 0;
+ }
meson_saradc_stop_sample_engine(priv);
@@ -711,6 +714,8 @@
.data = (ulong)&gxl_saradc_data },
{ .compatible = "amlogic,meson-gxm-saradc",
.data = (ulong)&gxl_saradc_data },
+ { .compatible = "amlogic,meson-g12a-saradc",
+ .data = (ulong)&gxl_saradc_data },
{ }
};
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 7e67895..e7c26db 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -4,18 +4,19 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <log.h>
#include <stm32_rcc.h>
-#include <linux/bitops.h>
-
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_pwr.h>
-
+#include <dm/device_compat.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
+#include <linux/bitops.h>
#define RCC_CR_HSION BIT(0)
#define RCC_CR_HSEON BIT(16)
@@ -309,7 +310,7 @@
>> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
break;
default:
- pr_err("incorrect PLLSAI output %d\n", output);
+ log_err("incorrect PLLSAI output %d\n", output);
return -EINVAL;
}
@@ -490,7 +491,7 @@
return (sysclk >> stm32_get_apb_shift(regs, APB2));
default:
- pr_err("clock index %ld out of range\n", clk->id);
+ dev_err(clk->dev, "clock index %ld out of range\n", clk->id);
return -EINVAL;
}
}
@@ -509,8 +510,9 @@
/* Only set_rate for LTDC clock is implemented */
if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
- pr_err("set_rate not implemented for clock index %ld\n",
- clk->id);
+ dev_err(clk->dev,
+ "set_rate not implemented for clock index %ld\n",
+ clk->id);
return 0;
}
@@ -604,8 +606,8 @@
u32 offset = clk->id / 32;
u32 bit_index = clk->id % 32;
- debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
- __func__, clk->id, offset, bit_index);
+ dev_dbg(clk->dev, "clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
+ clk->id, offset, bit_index);
setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
return 0;
@@ -618,7 +620,7 @@
struct clk clk;
int err;
- debug("%s\n", __func__);
+ dev_dbg(dev, "%s\n", __func__);
struct stm32_clk *priv = dev_get_priv(dev);
fdt_addr_t addr;
@@ -652,14 +654,14 @@
&fixed_clock_dev);
if (err) {
- pr_err("Can't find fixed clock (%d)", err);
+ dev_err(dev, "Can't find fixed clock (%d)", err);
return err;
}
err = clk_request(fixed_clock_dev, &clk);
if (err) {
- pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
- err);
+ dev_err(dev, "Can't request %s clk (%d)",
+ fixed_clock_dev->name, err);
return err;
}
@@ -673,8 +675,8 @@
priv->hse_rate = clk_get_rate(&clk);
if (priv->hse_rate < 1000000) {
- pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
- priv->hse_rate);
+ dev_err(dev, "unexpected HSE clock rate = %ld \"n",
+ priv->hse_rate);
return -EINVAL;
}
@@ -684,8 +686,7 @@
err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (err) {
- debug("%s: can't find syscon device (%d)\n", __func__,
- err);
+ dev_err(dev, "can't find syscon device (%d)\n", err);
return err;
}
@@ -699,10 +700,10 @@
static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
{
- debug("%s(clk=%p)\n", __func__, clk);
+ dev_dbg(clk->dev, "clk=%p\n", clk);
if (args->args_count != 2) {
- debug("Invaild args_count: %d\n", args->args_count);
+ dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}
diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index 0171fe8..20b3647 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
@@ -11,6 +13,7 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include <dm/root.h>
#include <linux/bitops.h>
@@ -465,18 +468,18 @@
int ret;
const char *name = pllsrc_name[pllsrc];
- debug("%s name %s\n", __func__, name);
+ log_debug("pllsrc name %s\n", name);
clk.id = 0;
ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);
if (ret) {
- pr_err("Can't find clk %s (%d)", name, ret);
+ log_err("Can't find clk %s (%d)", name, ret);
return 0;
}
ret = clk_request(fixed_clock_dev, &clk);
if (ret) {
- pr_err("Can't request %s clk (%d)", name, ret);
+ log_err("Can't request %s clk (%d)", name, ret);
return 0;
}
@@ -484,8 +487,7 @@
if (pllsrc == HSI)
divider = stm32_get_HSI_divider(regs);
- debug("%s divider %d rate %ld\n", __func__,
- divider, clk_get_rate(&clk));
+ log_debug("divider %d rate %ld\n", divider, clk_get_rate(&clk));
return clk_get_rate(&clk) >> divider;
};
@@ -516,7 +518,7 @@
break;
case RCC_PLLCKSELR_PLLSRC_NO_CLK:
/* shouldn't happen */
- pr_err("wrong value for RCC_PLLCKSELR register\n");
+ log_err("wrong value for RCC_PLLCKSELR register\n");
pllsrc = 0;
break;
}
@@ -546,10 +548,10 @@
vco = (pllsrc / divm1) * divn1;
rate = (pllsrc * fracn1) / (divm1 * 8192);
- debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
- __func__, divm1, divn1, divp1, divq1, divr1);
- debug("%s fracn1 = %d vco = %ld rate = %ld\n",
- __func__, fracn1, vco, rate);
+ log_debug("divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
+ divm1, divn1, divp1, divq1, divr1);
+ log_debug("fracn1 = %d vco = %ld rate = %ld\n",
+ fracn1, vco, rate);
switch (output) {
case PLL1_P_CK:
@@ -610,7 +612,7 @@
case 16:
return sysclk / 4;
default:
- pr_err("unexpected prescaler value (%d)\n", psc);
+ log_err("unexpected prescaler value (%d)\n", psc);
return 0;
}
else
@@ -623,7 +625,7 @@
case 16:
return sysclk / psc;
default:
- pr_err("unexpected prescaler value (%d)\n", psc);
+ log_err("unexpected prescaler value (%d)\n", psc);
return 0;
}
};
@@ -665,8 +667,8 @@
if (!sysclk)
return sysclk;
- debug("%s system clock: source = %d freq = %ld\n",
- __func__, source, sysclk);
+ dev_dbg(clk->dev, "system clock: source = %d freq = %ld\n",
+ source, sysclk);
d1cfgr = readl(®s->d1cfgr);
@@ -685,8 +687,8 @@
gate_offset = clk_map[clk->id].gate_offset;
- debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
- __func__, clk->id, gate_offset, sysclk);
+ dev_dbg(clk->dev, "clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
+ clk->id, gate_offset, sysclk);
switch (gate_offset) {
case RCC_AHB3ENR:
@@ -704,8 +706,8 @@
sysclk = sysclk / prescaler_table[idx];
}
- debug("%s system clock: freq after APB3 prescaler = %ld\n",
- __func__, sysclk);
+ dev_dbg(clk->dev, "system clock: freq after APB3 prescaler = %ld\n",
+ sysclk);
return sysclk;
break;
@@ -719,8 +721,9 @@
sysclk = sysclk / prescaler_table[idx];
}
- debug("%s system clock: freq after APB4 prescaler = %ld\n",
- __func__, sysclk);
+ dev_dbg(clk->dev,
+ "system clock: freq after APB4 prescaler = %ld\n",
+ sysclk);
return sysclk;
break;
@@ -741,8 +744,9 @@
return stm32_get_timer_rate(priv, sysclk, APB1);
}
- debug("%s system clock: freq after APB1 prescaler = %ld\n",
- __func__, sysclk);
+ dev_dbg(clk->dev,
+ "system clock: freq after APB1 prescaler = %ld\n",
+ sysclk);
return (sysclk / stm32_get_apb_psc(regs, APB1));
break;
@@ -758,15 +762,17 @@
return stm32_get_timer_rate(priv, sysclk, APB2);
}
- debug("%s system clock: freq after APB2 prescaler = %ld\n",
- __func__, sysclk);
+ dev_dbg(clk->dev,
+ "system clock: freq after APB2 prescaler = %ld\n",
+ sysclk);
return (sysclk / stm32_get_apb_psc(regs, APB2));
break;
default:
- pr_err("unexpected gate_offset value (0x%x)\n", gate_offset);
+ dev_err(clk->dev, "unexpected gate_offset value (0x%x)\n",
+ gate_offset);
return -EINVAL;
break;
}
@@ -783,9 +789,9 @@
gate_offset = clk_map[clk_id].gate_offset;
gate_bit_index = clk_map[clk_id].gate_bit_idx;
- debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
- __func__, clk->id, gate_offset, gate_bit_index,
- clk_map[clk_id].name);
+ dev_dbg(clk->dev, "clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
+ clk->id, gate_offset, gate_bit_index,
+ clk_map[clk_id].name);
setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index));
@@ -810,13 +816,13 @@
"st,syscfg", &syscon);
if (err) {
- pr_err("unable to find syscon device\n");
+ dev_err(dev, "unable to find syscon device\n");
return err;
}
priv->pwr_regmap = syscon_get_regmap(syscon);
if (!priv->pwr_regmap) {
- pr_err("unable to find regmap\n");
+ dev_err(dev, "unable to find regmap\n");
return -ENODEV;
}
@@ -829,7 +835,7 @@
struct ofnode_phandle_args *args)
{
if (args->args_count != 1) {
- debug("Invaild args_count: %d\n", args->args_count);
+ dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}
@@ -852,7 +858,7 @@
clk->id = 0;
}
- debug("%s clk->id %ld\n", __func__, clk->id);
+ dev_dbg(clk->dev, "clk->id %ld\n", clk->id);
return 0;
}
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 5bea2b6..d4f1048 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_CLK
+
#include <common.h>
#include <clk-uclass.h>
#include <div64.h>
@@ -14,12 +16,13 @@
#include <syscon.h>
#include <time.h>
#include <vsprintf.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device_compat.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/iopoll.h>
-#include <asm/arch/sys_proto.h>
-#include <dt-bindings/clock/stm32mp1-clks.h>
-#include <dt-bindings/clock/stm32mp1-clksrc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -781,7 +784,7 @@
static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
{
if (idx >= NB_OSC) {
- debug("%s: clk id %d not found\n", __func__, idx);
+ log_debug("clk id %d not found\n", idx);
return 0;
}
@@ -799,7 +802,7 @@
}
if (i == nb_clks) {
- printf("%s: clk id %d not found\n", __func__, (u32)id);
+ log_err("clk id %d not found\n", (u32)id);
return -EINVAL;
}
@@ -812,8 +815,7 @@
const struct stm32mp1_clk_gate *gate = priv->data->gate;
if (gate[i].sel > _PARENT_SEL_NB) {
- printf("%s: parents for clk id %d not found\n",
- __func__, i);
+ log_err("parents for clk id %d not found\n", i);
return -EINVAL;
}
@@ -858,17 +860,14 @@
p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
if (p < sel[s].nb_parent) {
-#ifdef DEBUG
- debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
- stm32mp1_clk_parent_name[sel[s].parent[p]],
- stm32mp1_clk_parent_sel_name[s],
- (u32)id);
-#endif
+ log_content("%s clock is the parent %s of clk id %d\n",
+ stm32mp1_clk_parent_name[sel[s].parent[p]],
+ stm32mp1_clk_parent_sel_name[s],
+ (u32)id);
return sel[s].parent[p];
}
- pr_err("%s: no parents defined for clk id %d\n",
- __func__, (u32)id);
+ log_err("no parents defined for clk id %d\n", (u32)id);
return -EINVAL;
}
@@ -1124,7 +1123,7 @@
if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
&dev)) {
if (clk_request(dev, &clk)) {
- pr_err("ck_dsi_phy request");
+ log_err("ck_dsi_phy request");
} else {
clk.id = 0;
clock = clk_get_rate(&clk);
@@ -1136,8 +1135,7 @@
break;
}
- debug("%s(%d) clock = %lx : %ld kHz\n",
- __func__, p, clock, clock / 1000);
+ log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000);
return clock;
}
@@ -1156,7 +1154,7 @@
else
setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
- debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
+ dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
return 0;
}
@@ -1177,7 +1175,7 @@
else
clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
- debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
+ dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
return 0;
}
@@ -1193,10 +1191,9 @@
rate = stm32mp1_clk_get(priv, p);
-#ifdef DEBUG
- debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
- __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
-#endif
+ dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n",
+ (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
+
return rate;
}
@@ -1335,7 +1332,7 @@
ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
if (ret) {
- debug("PLL1 OPP configuration not found (%d).\n", ret);
+ log_debug("PLL1 OPP configuration not found (%d).\n", ret);
return ret;
}
@@ -1440,8 +1437,8 @@
TIMEOUT_1S);
if (ret)
- pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
- mask_rdy, address, enable, readl(address));
+ log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
+ mask_rdy, address, enable, readl(address));
return ret;
}
@@ -1529,8 +1526,8 @@
val & RCC_OCRDYR_HSIDIVRDY,
TIMEOUT_200MS);
if (ret)
- pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
- address, readl(address));
+ log_err("HSIDIV failed @ 0x%x: 0x%x\n",
+ address, readl(address));
return ret;
}
@@ -1546,7 +1543,7 @@
break;
if (hsidiv == 4) {
- pr_err("clk-hsi frequency invalid");
+ log_err("clk-hsi frequency invalid");
return -1;
}
@@ -1577,8 +1574,8 @@
TIMEOUT_200MS);
if (ret) {
- pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
- pll_id, pllxcr, readl(pllxcr));
+ log_err("PLL%d start failed @ 0x%x: 0x%x\n",
+ pll_id, pllxcr, readl(pllxcr));
return ret;
}
@@ -1640,7 +1637,7 @@
if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
- debug("invalid refclk = %x\n", (u32)refclk);
+ log_err("invalid refclk = %x\n", (u32)refclk);
return -EINVAL;
}
if (type == PLL_800 && refclk >= 8000000)
@@ -1736,7 +1733,7 @@
divn = (value >> 13) - 1;
if (divn < DIVN_MIN ||
divn > stm32mp1_pll[type].divn_max) {
- pr_err("divn invalid = %d", divn);
+ dev_err(dev, "divn invalid = %d", divn);
return -EINVAL;
}
fracv = value - ((divn + 1) << 13);
@@ -1761,8 +1758,8 @@
ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
TIMEOUT_200MS);
if (ret)
- pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
- clksrc, address, readl(address));
+ log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
+ clksrc, address, readl(address));
return ret;
}
@@ -1781,7 +1778,7 @@
if (cntfid0 != rate) {
u64 counter;
- pr_debug("System Generic Counter (STGEN) update\n");
+ log_debug("System Generic Counter (STGEN) update\n");
clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
counter = (u64)readl(stgenc + STGENC_CNTCVL);
counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
@@ -1807,8 +1804,8 @@
ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
TIMEOUT_200MS);
if (ret)
- pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
- clkdiv, address, readl(address));
+ log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
+ clkdiv, address, readl(address));
return ret;
}
@@ -1891,13 +1888,13 @@
/* check mandatory field */
ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
if (ret < 0) {
- debug("field st,clksrc invalid: error %d\n", ret);
+ dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret);
return -FDT_ERR_NOTFOUND;
}
ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
if (ret < 0) {
- debug("field st,clkdiv invalid: error %d\n", ret);
+ dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret);
return -FDT_ERR_NOTFOUND;
}
@@ -1911,11 +1908,11 @@
pllcfg_valid[i] = ofnode_valid(node);
pllcsg_set[i] = false;
if (pllcfg_valid[i]) {
- debug("DT for PLL %d @ %s\n", i, name);
+ dev_dbg(dev, "DT for PLL %d @ %s\n", i, name);
ret = ofnode_read_u32_array(node, "cfg",
pllcfg[i], PLLCFG_NB);
if (ret < 0) {
- debug("field cfg invalid: error %d\n", ret);
+ dev_dbg(dev, "field cfg invalid: error %d\n", ret);
return -FDT_ERR_NOTFOUND;
}
pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
@@ -1925,30 +1922,30 @@
if (!ret) {
pllcsg_set[i] = true;
} else if (ret != -FDT_ERR_NOTFOUND) {
- debug("invalid csg node for pll@%d res=%d\n",
- i, ret);
+ dev_dbg(dev, "invalid csg node for pll@%d res=%d\n",
+ i, ret);
return ret;
}
} else if (i == _PLL1) {
/* use OPP for PLL1 for A7 CPU */
- debug("DT for PLL %d with OPP\n", i);
+ dev_dbg(dev, "DT for PLL %d with OPP\n", i);
ret = stm32mp1_pll1_opp(priv,
clksrc[CLKSRC_PLL12],
pllcfg[i],
&pllfracv[i]);
if (ret) {
- debug("PLL %d with OPP error = %d\n", i, ret);
+ dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret);
return ret;
}
pllcfg_valid[i] = true;
}
}
- debug("configuration MCO\n");
+ dev_dbg(dev, "configuration MCO\n");
stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
- debug("switch ON osillator\n");
+ dev_dbg(dev, "switch ON osillator\n");
/*
* switch ON oscillator found in device-tree,
* HSI already ON after bootrom
@@ -1986,24 +1983,24 @@
stm32mp1_csi_set(rcc, 1);
/* come back to HSI */
- debug("come back to HSI\n");
+ dev_dbg(dev, "come back to HSI\n");
set_clksrc(priv, CLK_MPU_HSI);
set_clksrc(priv, CLK_AXI_HSI);
set_clksrc(priv, CLK_MCU_HSI);
- debug("pll stop\n");
+ dev_dbg(dev, "pll stop\n");
for (i = 0; i < _PLL_NB; i++)
pll_stop(priv, i);
/* configure HSIDIV */
- debug("configure HSIDIV\n");
+ dev_dbg(dev, "configure HSIDIV\n");
if (priv->osc[_HSI]) {
stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
stgen_config(priv);
}
/* select DIV */
- debug("select DIV\n");
+ dev_dbg(dev, "select DIV\n");
/* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
@@ -2018,17 +2015,17 @@
writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
/* configure PLLs source */
- debug("configure PLLs source\n");
+ dev_dbg(dev, "configure PLLs source\n");
set_clksrc(priv, clksrc[CLKSRC_PLL12]);
set_clksrc(priv, clksrc[CLKSRC_PLL3]);
set_clksrc(priv, clksrc[CLKSRC_PLL4]);
/* configure and start PLLs */
- debug("configure PLLs\n");
+ dev_dbg(dev, "configure PLLs\n");
for (i = 0; i < _PLL_NB; i++) {
if (!pllcfg_valid[i])
continue;
- debug("configure PLL %d\n", i);
+ dev_dbg(dev, "configure PLL %d\n", i);
pll_config(priv, i, pllcfg[i], pllfracv[i]);
if (pllcsg_set[i])
pll_csg(priv, i, pllcsg[i]);
@@ -2039,7 +2036,7 @@
for (i = 0; i < _PLL_NB; i++) {
if (!pllcfg_valid[i])
continue;
- debug("output PLL %d\n", i);
+ dev_dbg(dev, "output PLL %d\n", i);
pll_output(priv, i, pllcfg[i][PLLCFG_O]);
}
@@ -2048,14 +2045,14 @@
stm32mp1_lse_wait(rcc);
/* configure with expected clock source */
- debug("CLKSRC\n");
+ dev_dbg(dev, "CLKSRC\n");
set_clksrc(priv, clksrc[CLKSRC_MPU]);
set_clksrc(priv, clksrc[CLKSRC_AXI]);
set_clksrc(priv, clksrc[CLKSRC_MCU]);
set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
/* configure PKCK */
- debug("PKCK\n");
+ dev_dbg(dev, "PKCK\n");
pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
if (pkcs_cell) {
bool ckper_disabled = false;
@@ -2081,7 +2078,7 @@
/* STGEN clock source can change with CLK_STGEN_XXX */
stgen_config(priv);
- debug("oscillator off\n");
+ dev_dbg(dev, "oscillator off\n");
/* switch OFF HSI if not found in device-tree */
if (!priv->osc[_HSI])
stm32mp1_hsi_set(rcc, 0);
@@ -2147,14 +2144,12 @@
case DSI_PX:
break;
default:
- pr_err("not supported");
+ dev_err(clk->dev, "Set of clk %ld not supported", clk->id);
return -EINVAL;
}
p = stm32mp1_clk_get_parent(priv, clk->id);
-#ifdef DEBUG
- debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
-#endif
+ dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]);
if (p < 0)
return -EINVAL;
@@ -2192,7 +2187,7 @@
clk.id = 0;
if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
if (clk_request(dev, &clk))
- pr_err("%s request", name);
+ log_err("%s request", name);
else
priv->osc[index] = clk_get_rate(&clk);
}
@@ -2214,7 +2209,7 @@
for (i = 0; i < NB_OSC; i++) {
stm32mp1_osc_clk_init(name[i], priv, i);
- debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
+ dev_dbg(dev, "%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
}
}
@@ -2288,11 +2283,11 @@
if (!(gd->flags & GD_FLG_RELOC))
result = stm32mp1_clktree(dev);
if (result)
- printf("clock tree initialization failed (%d)\n", result);
+ dev_err(dev, "clock tree initialization failed (%d)\n", result);
#endif
#ifndef CONFIG_SPL_BUILD
-#if defined(DEBUG)
+#if defined(VERBOSE_DEBUG)
/* display debug information for probe after relocation */
if (gd->flags & GD_FLG_RELOC)
stm32mp1_clk_dump(priv);
@@ -2306,14 +2301,14 @@
if (gd->flags & GD_FLG_RELOC) {
char buf[32];
- printf("Clocks:\n");
- printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
- printf("- MCU : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
- printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
- printf("- PER : %s MHz\n",
- strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
- printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
+ log_info("Clocks:\n");
+ log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
+ log_info("- MCU : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
+ log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
+ log_info("- PER : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
+ log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
}
#endif /* CONFIG_DISPLAY_CPUINFO */
#endif
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index c873d69..7204383 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,4 +6,5 @@
obj-$(CONFIG_CLK_MESON_GX) += gxbb.o
obj-$(CONFIG_CLK_MESON_AXG) += axg.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a.o
+obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o
diff --git a/drivers/clk/meson/g12a-ao.c b/drivers/clk/meson/g12a-ao.c
new file mode 100644
index 0000000..0148529
--- /dev/null
+++ b/drivers/clk/meson/g12a-ao.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <dt-bindings/clock/g12a-aoclkc.h>
+
+#include "clk_meson.h"
+
+struct meson_clk {
+ struct regmap *map;
+};
+
+#define AO_CLK_GATE0 0x4c
+#define AO_SAR_CLK 0x90
+
+static struct meson_gate gates[] = {
+ MESON_GATE(CLKID_AO_SAR_ADC, AO_CLK_GATE0, 8),
+ MESON_GATE(CLKID_AO_SAR_ADC_CLK, AO_SAR_CLK, 8),
+};
+
+static int meson_set_gate(struct clk *clk, bool on)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct meson_gate *gate;
+
+ if (clk->id >= ARRAY_SIZE(gates))
+ return -ENOENT;
+
+ gate = &gates[clk->id];
+
+ if (gate->reg == 0)
+ return 0;
+
+ regmap_update_bits(priv->map, gate->reg,
+ BIT(gate->bit), on ? BIT(gate->bit) : 0);
+
+ return 0;
+}
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate(clk, true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate(clk, false);
+}
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
+ if (IS_ERR(priv->map))
+ return PTR_ERR(priv->map);
+
+ return 0;
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+};
+
+static const struct udevice_id meson_clk_ids[] = {
+ { .compatible = "amlogic,meson-g12a-aoclkc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk_axg) = {
+ .name = "meson_clk_g12a_ao",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index 79d55e8..7184db3 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -4,6 +4,8 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_GPIO
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -331,7 +333,7 @@
dev_err(dev, "failed to enable clock\n");
return ret;
}
- debug("clock enabled for device %s\n", dev->name);
+ dev_dbg(dev, "clock enabled\n");
return 0;
}
diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c
index fdc1f6f..46ed646 100644
--- a/drivers/hwspinlock/stm32_hwspinlock.c
+++ b/drivers/hwspinlock/stm32_hwspinlock.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_HWSPINLOCK
+
#include <common.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index 6553bdc..7b04a09 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -3,6 +3,8 @@
* (C) Copyright 2017 STMicroelectronics
*/
+#define LOG_CATEGORY UCLASS_I2C
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -11,10 +13,10 @@
#include <regmap.h>
#include <reset.h>
#include <syscon.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
-
-#include <dm/device.h>
#include <linux/err.h>
#include <linux/io.h>
@@ -346,7 +348,7 @@
*status = readl(®s->isr);
while (!(*status & flags)) {
if (get_timer(time_start) > CONFIG_SYS_HZ) {
- debug("%s: i2c timeout\n", __func__);
+ log_debug("i2c timeout\n");
return -ETIMEDOUT;
}
@@ -369,7 +371,7 @@
return ret;
if (status & STM32_I2C_ISR_BERR) {
- debug("%s: Bus error\n", __func__);
+ log_debug("Bus error\n");
/* Clear BERR flag */
setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF);
@@ -378,7 +380,7 @@
}
if (status & STM32_I2C_ISR_ARLO) {
- debug("%s: Arbitration lost\n", __func__);
+ log_debug("Arbitration lost\n");
/* Clear ARLO flag */
setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF);
@@ -387,7 +389,7 @@
}
if (status & STM32_I2C_ISR_NACKF) {
- debug("%s: Receive NACK\n", __func__);
+ log_debug("Receive NACK\n");
/* Clear NACK flag */
setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF);
@@ -535,8 +537,8 @@
if (sdadel_max < 0)
sdadel_max = 0;
- debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__,
- sdadel_min, sdadel_max, scldel_min);
+ log_debug("SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
+ sdadel_min, sdadel_max, scldel_min);
/* Compute possible values for PRESC, SCLDEL and SDADEL */
for (p = 0; p < STM32_PRESC_MAX; p++) {
@@ -572,7 +574,7 @@
}
if (list_empty(solutions)) {
- pr_err("%s: no Prescaler solution\n", __func__);
+ log_err("no Prescaler solution\n");
ret = -EPERM;
}
@@ -656,7 +658,7 @@
}
if (!sol_found) {
- pr_err("%s: no solution at all\n", __func__);
+ log_err("no solution at all\n");
ret = -EPERM;
}
@@ -686,23 +688,22 @@
specs = get_specs(setup->speed_freq);
if (specs == ERR_PTR(-EINVAL)) {
- pr_err("%s: speed out of bound {%d}\n", __func__,
- setup->speed_freq);
+ log_err("speed out of bound {%d}\n",
+ setup->speed_freq);
return -EINVAL;
}
if (setup->rise_time > specs->rise_max ||
setup->fall_time > specs->fall_max) {
- pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
- __func__,
- setup->rise_time, specs->rise_max,
- setup->fall_time, specs->fall_max);
+ log_err("timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
+ setup->rise_time, specs->rise_max,
+ setup->fall_time, specs->fall_max);
return -EINVAL;
}
if (setup->dnf > STM32_I2C_DNF_MAX) {
- pr_err("%s: DNF out of bound %d/%d\n", __func__,
- setup->dnf, STM32_I2C_DNF_MAX);
+ log_err("DNF out of bound %d/%d\n",
+ setup->dnf, STM32_I2C_DNF_MAX);
return -EINVAL;
}
@@ -715,10 +716,10 @@
if (ret)
goto exit;
- debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
- __func__, output->presc,
- output->scldel, output->sdadel,
- output->scll, output->sclh);
+ log_debug("Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
+ output->presc,
+ output->scldel, output->sdadel,
+ output->scll, output->sclh);
exit:
/* Release list and memory */
@@ -751,20 +752,19 @@
setup->clock_src = clk_get_rate(&i2c_priv->clk);
if (!setup->clock_src) {
- pr_err("%s: clock rate is 0\n", __func__);
+ log_err("clock rate is 0\n");
return -EINVAL;
}
do {
ret = stm32_i2c_compute_timing(i2c_priv, setup, timing);
if (ret) {
- debug("%s: failed to compute I2C timings.\n",
- __func__);
+ log_debug("failed to compute I2C timings.\n");
if (setup->speed_freq > I2C_SPEED_STANDARD_RATE) {
setup->speed_freq =
get_lower_rate(setup->speed_freq);
- debug("%s: downgrade I2C Speed Freq to (%i)\n",
- __func__, setup->speed_freq);
+ log_debug("downgrade I2C Speed Freq to (%i)\n",
+ setup->speed_freq);
} else {
break;
}
@@ -772,16 +772,16 @@
} while (ret);
if (ret) {
- pr_err("%s: impossible to compute I2C timings.\n", __func__);
+ log_err("impossible to compute I2C timings.\n");
return ret;
}
- debug("%s: I2C Freq(%i), Clk Source(%i)\n", __func__,
- setup->speed_freq, setup->clock_src);
- debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__,
- setup->rise_time, setup->fall_time);
- debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__,
- setup->analog_filter ? "On" : "Off", setup->dnf);
+ log_debug("I2C Freq(%i), Clk Source(%i)\n",
+ setup->speed_freq, setup->clock_src);
+ log_debug("I2C Rise(%i) and Fall(%i) Time\n",
+ setup->rise_time, setup->fall_time);
+ log_debug("I2C Analog Filter(%s), DNF(%i)\n",
+ setup->analog_filter ? "On" : "Off", setup->dnf);
i2c_priv->speed = setup->speed_freq;
@@ -848,12 +848,12 @@
return 0;
}
-static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+static int stm32_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
- struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus);
+ struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev);
if (speed > I2C_SPEED_FAST_PLUS_RATE) {
- debug("%s: Speed %d not supported\n", __func__, speed);
+ dev_dbg(dev, "Speed %d not supported\n", speed);
return -EINVAL;
}
diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c
index 093b570..69c86e0 100644
--- a/drivers/mailbox/stm32-ipcc.c
+++ b/drivers/mailbox/stm32-ipcc.c
@@ -3,6 +3,8 @@
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_MAILBOX
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -44,11 +46,11 @@
{
struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
- debug("%s(chan=%p)\n", __func__, chan);
+ dev_dbg(chan->dev, "chan=%p\n", chan);
if (chan->id >= ipcc->n_chans) {
- debug("%s failed to request channel: %ld\n",
- __func__, chan->id);
+ dev_dbg(chan->dev, "failed to request channel: %ld\n",
+ chan->id);
return -EINVAL;
}
@@ -57,7 +59,7 @@
static int stm32_ipcc_free(struct mbox_chan *chan)
{
- debug("%s(chan=%p)\n", __func__, chan);
+ dev_dbg(chan->dev, "chan=%p\n", chan);
return 0;
}
@@ -66,7 +68,7 @@
{
struct stm32_ipcc *ipcc = dev_get_priv(chan->dev);
- debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+ dev_dbg(chan->dev, "chan=%p, data=%p\n", chan, data);
if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id))
return -EBUSY;
@@ -83,7 +85,7 @@
u32 val;
int proc_offset;
- debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+ dev_dbg(chan->dev, "chan=%p, data=%p\n", chan, data);
/* read 'channel occupied' status from other proc */
proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
@@ -104,7 +106,7 @@
struct clk clk;
int ret;
- debug("%s(dev=%p)\n", __func__, dev);
+ dev_dbg(dev, "\n");
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c
index f3f48f8..212bb4f 100644
--- a/drivers/memory/stm32-fmc2-ebi.c
+++ b/drivers/memory/stm32-fmc2-ebi.c
@@ -3,10 +3,13 @@
* Copyright (C) STMicroelectronics 2020
*/
+#define LOG_CATEGORY UCLASS_NOP
+
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <reset.h>
+#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/iopoll.h>
@@ -860,7 +863,7 @@
u32 setup = 0;
if (!prop->set) {
- pr_err("property %s is not well defined\n", prop->name);
+ log_err("property %s is not well defined\n", prop->name);
return -EINVAL;
}
@@ -873,8 +876,8 @@
bprop = ofnode_read_bool(node, prop->name);
if (prop->mprop && !bprop) {
- pr_err("mandatory property %s not defined in the device tree\n",
- prop->name);
+ log_err("mandatory property %s not defined in the device tree\n",
+ prop->name);
return -EINVAL;
}
@@ -886,8 +889,8 @@
ret = ofnode_read_u32(node, prop->name, &val);
if (prop->mprop && ret) {
- pr_err("mandatory property %s not defined in the device tree\n",
- prop->name);
+ log_err("mandatory property %s not defined in the device tree\n",
+ prop->name);
return ret;
}
@@ -949,8 +952,8 @@
ret = stm32_fmc2_ebi_parse_prop(ebi, node, p, cs);
if (ret) {
- pr_err("property %s could not be set: %d\n",
- p->name, ret);
+ log_err("property %s could not be set: %d\n",
+ p->name, ret);
return ret;
}
}
@@ -971,25 +974,24 @@
dev_for_each_subnode(child, dev) {
ret = ofnode_read_u32(child, "reg", &bank);
if (ret) {
- pr_err("could not retrieve reg property: %d\n", ret);
+ dev_err(dev, "could not retrieve reg property: %d\n", ret);
return ret;
}
if (bank >= FMC2_MAX_BANKS) {
- pr_err("invalid reg value: %d\n", bank);
+ dev_err(dev, "invalid reg value: %d\n", bank);
return -EINVAL;
}
if (ebi->bank_assigned & BIT(bank)) {
- pr_err("bank already assigned: %d\n", bank);
+ dev_err(dev, "bank already assigned: %d\n", bank);
return -EINVAL;
}
if (bank < FMC2_MAX_EBI_CE) {
ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
if (ret) {
- pr_err("setup chip select %d failed: %d\n",
- bank, ret);
+ dev_err(dev, "setup chip select %d failed: %d\n", bank, ret);
return ret;
}
}
@@ -999,12 +1001,12 @@
}
if (!child_found) {
- pr_warn("no subnodes found, disable the driver.\n");
+ dev_warn(dev, "no subnodes found, disable the driver.\n");
return -ENODEV;
}
if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
- pr_err("NWAIT signal connected to EBI and NAND controllers\n");
+ dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
return -EINVAL;
}
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index 8627545..f14d6e2 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_NOP
+
#include <common.h>
#include <dm.h>
#include <log.h>
@@ -45,14 +47,14 @@
(struct stm32_rcc_clk *)dev_get_driver_data(dev);
int ret;
- debug("%s(dev=%p)\n", __func__, dev);
+ dev_dbg(dev, "RCC bind\n");
drv = lists_driver_lookup_name(rcc_clk->drv_name);
if (!drv) {
- debug("Cannot find driver '%s'\n", rcc_clk->drv_name);
+ dev_err(dev, "Cannot find driver '%s'\n", rcc_clk->drv_name);
return -ENOENT;
}
- ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name,
+ ret = device_bind_with_driver_data(dev, drv, dev->name,
rcc_clk->soc,
dev_ofnode(dev), &child);
@@ -65,7 +67,7 @@
return -ENOENT;
}
- return device_bind_with_driver_data(dev, drv, "stm32_rcc_reset",
+ return device_bind_with_driver_data(dev, drv, dev->name,
rcc_clk->soc,
dev_ofnode(dev), &child);
}
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index 3246f6b..a3cdf7b 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_MMC
+
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
@@ -13,6 +15,7 @@
#include <malloc.h>
#include <asm/bitops.h>
#include <asm/cache.h>
+#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
@@ -200,10 +203,11 @@
#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
#define SDMMC_BUSYD0END_TIMEOUT_US 2000000
-static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
+static void stm32_sdmmc2_start_data(struct udevice *dev,
struct mmc_data *data,
struct stm32_sdmmc2_ctx *ctx)
{
+ struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
u32 data_ctrl, idmabase0;
/* Configure the SDMMC DPSM (Data Path State Machine) */
@@ -241,10 +245,11 @@
writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
}
-static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
+static void stm32_sdmmc2_start_cmd(struct udevice *dev,
struct mmc_cmd *cmd, u32 cmd_param,
struct stm32_sdmmc2_ctx *ctx)
{
+ struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
u32 timeout = 0;
if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
@@ -290,10 +295,11 @@
writel(cmd_param, priv->base + SDMMC_CMD);
}
-static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
+static int stm32_sdmmc2_end_cmd(struct udevice *dev,
struct mmc_cmd *cmd,
struct stm32_sdmmc2_ctx *ctx)
{
+ struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
u32 mask = SDMMC_STA_CTIMEOUT;
u32 status;
int ret;
@@ -311,22 +317,22 @@
10000);
if (ret < 0) {
- debug("%s: timeout reading SDMMC_STA register\n", __func__);
+ dev_dbg(dev, "timeout reading SDMMC_STA register\n");
ctx->dpsm_abort = true;
return ret;
}
/* Check status */
if (status & SDMMC_STA_CTIMEOUT) {
- debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
- debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EILSEQ;
}
@@ -350,15 +356,15 @@
SDMMC_BUSYD0END_TIMEOUT_US);
if (ret < 0) {
- debug("%s: timeout reading SDMMC_STA\n",
- __func__);
+ dev_dbg(dev, "timeout reading SDMMC_STA\n");
ctx->dpsm_abort = true;
return ret;
}
if (status & SDMMC_STA_DTIMEOUT) {
- debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
- __func__, status);
+ dev_dbg(dev,
+ "error SDMMC_STA_DTIMEOUT (0x%x)\n",
+ status);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
@@ -368,11 +374,12 @@
return 0;
}
-static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
+static int stm32_sdmmc2_end_data(struct udevice *dev,
struct mmc_cmd *cmd,
struct mmc_data *data,
struct stm32_sdmmc2_ctx *ctx)
{
+ struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
u32 status;
@@ -394,37 +401,37 @@
invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
if (status & SDMMC_STA_DCRCFAIL) {
- debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
if (readl(priv->base + SDMMC_DCOUNT))
ctx->dpsm_abort = true;
return -EILSEQ;
}
if (status & SDMMC_STA_DTIMEOUT) {
- debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -ETIMEDOUT;
}
if (status & SDMMC_STA_TXUNDERR) {
- debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
if (status & SDMMC_STA_RXOVERR) {
- debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
if (status & SDMMC_STA_IDMATE) {
- debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
- __func__, status, cmd->cmdidx);
+ dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
+ status, cmd->cmdidx);
ctx->dpsm_abort = true;
return -EIO;
}
@@ -448,19 +455,18 @@
if (data) {
ctx.data_length = data->blocks * data->blocksize;
- stm32_sdmmc2_start_data(priv, data, &ctx);
+ stm32_sdmmc2_start_data(dev, data, &ctx);
}
- stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
+ stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx);
- debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
- __func__, cmd->cmdidx,
- data ? ctx.data_length : 0, (unsigned int)data);
+ dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n",
+ cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data);
- ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
+ ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx);
if (data && !ret)
- ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
+ ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx);
/* Clear flags */
writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
@@ -478,26 +484,24 @@
stop_cmd.cmdarg = 0;
stop_cmd.resp_type = MMC_RSP_R1b;
- debug("%s: send STOP command to abort dpsm treatments\n",
- __func__);
+ dev_dbg(dev, "send STOP command to abort dpsm treatments\n");
ctx.data_length = 0;
- stm32_sdmmc2_start_cmd(priv, &stop_cmd,
+ stm32_sdmmc2_start_cmd(dev, &stop_cmd,
SDMMC_CMD_CMDSTOP, &ctx);
- stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
+ stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx);
writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
}
if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
- printf("%s: cmd %d failed, retrying ...\n",
- __func__, cmd->cmdidx);
+ dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx);
retry--;
goto retry_cmd;
}
- debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
+ dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret);
return ret;
}
@@ -579,8 +583,8 @@
u32 sys_clock = clk_get_rate(&priv->clk);
u32 clk = 0;
- debug("%s: bus_with = %d, clock = %d\n", __func__,
- mmc->bus_width, mmc->clock);
+ dev_dbg(dev, "bus_with = %d, clock = %d\n",
+ mmc->bus_width, mmc->clock);
if (mmc->clk_disable)
stm32_sdmmc2_pwrcycle(priv);
@@ -616,7 +620,7 @@
{
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
- debug("stm32_sdmmc2_getcd called\n");
+ dev_dbg(dev, "%s called\n", __func__);
if (dm_gpio_is_valid(&priv->cd_gpio))
return dm_gpio_get_value(&priv->cd_gpio);
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index b8561b2..fd81a95 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -4,12 +4,15 @@
* Author: Christophe Kerello <christophe.kerello@st.com>
*/
+#define LOG_CATEGORY UCLASS_MTD
+
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <nand.h>
#include <reset.h>
+#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/delay.h>
@@ -324,7 +327,7 @@
ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr,
sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S);
if (ret < 0) {
- pr_err("Ham timeout\n");
+ log_err("Ham timeout\n");
return ret;
}
@@ -409,7 +412,7 @@
ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S);
if (ret < 0) {
- pr_err("Bch timeout\n");
+ log_err("Bch timeout\n");
return ret;
}
@@ -457,7 +460,7 @@
ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr,
bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S);
if (ret < 0) {
- pr_err("Bch timeout\n");
+ log_err("Bch timeout\n");
return ret;
}
@@ -795,26 +798,24 @@
nand->ncs /= sizeof(u32);
if (!nand->ncs) {
- pr_err("Invalid reg property size\n");
+ log_err("Invalid reg property size\n");
return -EINVAL;
}
ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs);
if (ret < 0) {
- pr_err("Could not retrieve reg property\n");
+ log_err("Could not retrieve reg property\n");
return -EINVAL;
}
for (i = 0; i < nand->ncs; i++) {
if (cs[i] >= FMC2_MAX_CE) {
- pr_err("Invalid reg value: %d\n",
- nand->cs_used[i]);
+ log_err("Invalid reg value: %d\n", nand->cs_used[i]);
return -EINVAL;
}
if (nfc->cs_assigned & BIT(cs[i])) {
- pr_err("Cs already assigned: %d\n",
- nand->cs_used[i]);
+ log_err("Cs already assigned: %d\n", nand->cs_used[i]);
return -EINVAL;
}
@@ -837,12 +838,12 @@
nchips++;
if (!nchips) {
- pr_err("NAND chip not defined\n");
+ log_err("NAND chip not defined\n");
return -EINVAL;
}
if (nchips > 1) {
- pr_err("Too many NAND chips defined\n");
+ log_err("Too many NAND chips defined\n");
return -EINVAL;
}
@@ -918,24 +919,21 @@
addr = dev_read_addr_index(dev, mem_region);
if (addr == FDT_ADDR_T_NONE) {
- pr_err("Resource data_base not found for cs%d",
- chip_cs);
+ dev_err(dev, "Resource data_base not found for cs%d", chip_cs);
return ret;
}
nfc->data_base[chip_cs] = addr;
addr = dev_read_addr_index(dev, mem_region + 1);
if (addr == FDT_ADDR_T_NONE) {
- pr_err("Resource cmd_base not found for cs%d",
- chip_cs);
+ dev_err(dev, "Resource cmd_base not found for cs%d", chip_cs);
return ret;
}
nfc->cmd_base[chip_cs] = addr;
addr = dev_read_addr_index(dev, mem_region + 2);
if (addr == FDT_ADDR_T_NONE) {
- pr_err("Resource addr_base not found for cs%d",
- chip_cs);
+ dev_err(dev, "Resource addr_base not found for cs%d", chip_cs);
return ret;
}
nfc->addr_base[chip_cs] = addr;
@@ -985,14 +983,14 @@
* ECC sector size = 512
*/
if (chip->ecc.mode != NAND_ECC_HW) {
- pr_err("Nand_ecc_mode is not well defined in the DT\n");
+ dev_err(dev, "Nand_ecc_mode is not well defined in the DT\n");
return -EINVAL;
}
ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps,
mtd->oobsize - FMC2_BBM_LEN);
if (ret) {
- pr_err("No valid ECC settings set\n");
+ dev_err(dev, "No valid ECC settings set\n");
return ret;
}
@@ -1045,6 +1043,6 @@
DM_DRIVER_GET(stm32_fmc2_nfc),
&dev);
if (ret && ret != -ENODEV)
- pr_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
- ret);
+ log_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n",
+ ret);
}
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index f23aef4..02d859a 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_PHY
+
#include <common.h>
#include <clk.h>
#include <div64.h>
@@ -98,8 +100,8 @@
u32 usbphyc_pll;
if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
- pr_debug("%s: input clk freq (%dHz) out of range\n",
- __func__, clk_rate);
+ log_debug("input clk freq (%dHz) out of range\n",
+ clk_rate);
return -EINVAL;
}
@@ -116,8 +118,8 @@
writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
- pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
- clk_rate, pll_params.ndiv, pll_params.frac);
+ log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
+ clk_rate, pll_params.ndiv, pll_params.frac);
return 0;
}
@@ -154,7 +156,7 @@
true : false;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
/* Check if one phy port has already configured the pll */
if (pllen && stm32_usbphyc_is_init(usbphyc))
goto initialized;
@@ -200,7 +202,7 @@
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->init = false;
/* Check if other phy port requires pllen */
@@ -239,7 +241,7 @@
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
if (usbphyc_phy->vdd) {
ret = regulator_set_enable(usbphyc_phy->vdd, true);
if (ret)
@@ -262,7 +264,7 @@
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->powered = false;
if (stm32_usbphyc_is_powered(usbphyc))
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 591cd1a..a1f53a7 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -3,6 +3,8 @@
* Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_PINCTRL
+
#include <common.h>
#include <dm.h>
#include <hwspinlock.h>
@@ -256,8 +258,8 @@
/* hwspinlock property is optional, just log the error */
ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
if (ret)
- debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
- __func__, ret);
+ dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n",
+ ret);
return 0;
}
@@ -305,8 +307,7 @@
{
gpio_dsc->port = (port_pin & 0x1F000) >> 12;
gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
- debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
- gpio_dsc->pin);
+ log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin);
return 0;
}
@@ -347,9 +348,9 @@
else
gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
- debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
- __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
- gpio_ctl->pupd);
+ log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
+ gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
+ gpio_ctl->pupd);
return 0;
}
@@ -373,7 +374,7 @@
if (rv < 0)
return rv;
len = rv / sizeof(pin_mux[0]);
- debug("%s: no of pinmux entries= %d\n", __func__, len);
+ log_debug("No of pinmux entries= %d\n", len);
if (len > MAX_PINS_ONE_IP)
return -EINVAL;
rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
@@ -382,7 +383,7 @@
for (i = 0; i < len; i++) {
struct gpio_desc desc;
- debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
+ log_debug("pinmux = %x\n", *(pin_mux + i));
prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
rv = uclass_get_device_by_seq(UCLASS_GPIO,
@@ -392,7 +393,7 @@
return rv;
desc.offset = gpio_dsc.pin;
rv = stm32_gpio_config(&desc, &gpio_ctl);
- debug("%s: rv = %d\n\n", __func__, rv);
+ log_debug("rv = %d\n\n", rv);
if (rv)
return rv;
}
@@ -408,7 +409,7 @@
int ret;
dev_for_each_subnode(node, dev) {
- debug("%s: bind %s\n", __func__, ofnode_get_name(node));
+ dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
ofnode_get_property(node, "gpio-controller", &ret);
if (ret < 0)
@@ -424,7 +425,7 @@
if (ret)
return ret;
- debug("%s: bind %s\n", __func__, name);
+ dev_dbg(dev, "bind %s\n", name);
}
return 0;
@@ -448,7 +449,7 @@
if (!list)
return -EINVAL;
- debug("%s: periph->name = %s\n", __func__, periph->name);
+ dev_dbg(dev, "periph->name = %s\n", periph->name);
size /= sizeof(*list);
for (i = 0; i < size; i++) {
@@ -456,7 +457,8 @@
config_node = ofnode_get_by_phandle(phandle);
if (!ofnode_valid(config_node)) {
- pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
+ dev_err(periph,
+ "prop pinctrl-0 index %d invalid phandle\n", i);
return -EINVAL;
}
diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c
index ef8274c..a4d50e7 100644
--- a/drivers/power/domain/meson-ee-pwrc.c
+++ b/drivers/power/domain/meson-ee-pwrc.c
@@ -13,7 +13,9 @@
#include <syscon.h>
#include <reset.h>
#include <clk.h>
+#include <dt-bindings/power/meson-axg-power.h>
#include <dt-bindings/power/meson-g12a-power.h>
+#include <dt-bindings/power/meson-gxbb-power.h>
#include <dt-bindings/power/meson-sm1-power.h>
#include <linux/bitops.h>
#include <linux/delay.h>
@@ -68,7 +70,7 @@
/* TOP Power Domains */
-static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
+static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = {
.sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
.sleep_mask = BIT(8),
.iso_reg = AO_RTI_GEN_PWR_SLEEP0,
@@ -126,6 +128,17 @@
VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
};
+static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_vpu[] = {
+ VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
+ VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
+};
+
+static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = {
+ VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
+ VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
+ VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
+};
+
static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
{ HHI_MEM_PD_REG0, GENMASK(3, 2) },
};
@@ -159,6 +172,10 @@
{ HHI_MEM_PD_REG0, GENMASK(25, 18) },
};
+static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_audio[] = {
+ { HHI_MEM_PD_REG0, GENMASK(5, 4) },
+};
+
static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
{ HHI_MEM_PD_REG0, GENMASK(5, 4) },
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
@@ -201,11 +218,24 @@
static bool pwrc_ee_get_power(struct power_domain *power_domain);
static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
- [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
+ [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
pwrc_ee_get_power, 11, 2),
[PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
};
+static struct meson_ee_pwrc_domain_desc axg_pwrc_domains[] = {
+ [PWRC_AXG_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, axg_pwrc_mem_vpu,
+ pwrc_ee_get_power, 5, 2),
+ [PWRC_AXG_ETHERNET_MEM_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
+ [PWRC_AXG_AUDIO_ID] = MEM_PD("AUDIO", axg_pwrc_mem_audio),
+};
+
+static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
+ [PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu,
+ pwrc_ee_get_power, 12, 2),
+ [PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
+};
+
static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
[PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
pwrc_ee_get_power, 11, 2),
@@ -369,6 +399,16 @@
.domains = g12a_pwrc_domains,
};
+static struct meson_ee_pwrc_domain_data meson_ee_axg_pwrc_data = {
+ .count = ARRAY_SIZE(axg_pwrc_domains),
+ .domains = axg_pwrc_domains,
+};
+
+static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = {
+ .count = ARRAY_SIZE(gxbb_pwrc_domains),
+ .domains = gxbb_pwrc_domains,
+};
+
static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
.count = ARRAY_SIZE(sm1_pwrc_domains),
.domains = sm1_pwrc_domains,
@@ -380,6 +420,14 @@
.data = (unsigned long)&meson_ee_g12a_pwrc_data,
},
{
+ .compatible = "amlogic,meson-gxbb-pwrc",
+ .data = (unsigned long)&meson_ee_gxbb_pwrc_data,
+ },
+ {
+ .compatible = "amlogic,meson-axg-pwrc",
+ .data = (unsigned long)&meson_ee_axg_pwrc_data,
+ },
+ {
.compatible = "amlogic,meson-sm1-pwrc",
.data = (unsigned long)&meson_ee_sm1_pwrc_data,
},
diff --git a/drivers/power/regulator/stm32-vrefbuf.c b/drivers/power/regulator/stm32-vrefbuf.c
index c2c5770..c37998a 100644
--- a/drivers/power/regulator/stm32-vrefbuf.c
+++ b/drivers/power/regulator/stm32-vrefbuf.c
@@ -6,6 +6,8 @@
* Originally based on the Linux kernel v4.16 drivers/regulator/stm32-vrefbuf.c
*/
+#define LOG_CATEGORY UCLASS_REGULATOR
+
#include <common.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 4003db0..540ad85 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -4,6 +4,8 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -272,7 +274,7 @@
ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (ret) {
- dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
+ dev_dbg(dev, "can't find syscon device (%d)\n", ret);
} else {
syscfg_base = (u32 *)ofnode_get_addr(args.node);
@@ -281,7 +283,7 @@
/* set memory mapping selection */
clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
} else {
- dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
+ dev_dbg(dev, "cannot find st,mem_remap property\n");
}
swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
@@ -289,7 +291,7 @@
/* set fmc swapping selection */
clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
} else {
- dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
+ dev_dbg(dev, "cannot find st,swp_fmc property\n");
}
dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
@@ -348,7 +350,7 @@
}
params->no_sdram_banks = bank;
- debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+ dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks);
return 0;
}
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
index bf3a4c9..0457166 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <clk.h>
#include <log.h>
@@ -311,17 +313,17 @@
u32 base_addr = get_base_addr(priv, base);
const struct reg_desc *desc = ddr_registers[type].desc;
- debug("init %s\n", ddr_registers[type].name);
+ log_debug("init %s\n", ddr_registers[type].name);
for (i = 0; i < ddr_registers[type].size; i++) {
ptr = (unsigned int *)(base_addr + desc[i].offset);
if (desc[i].par_offset == INVALID_OFFSET) {
- pr_err("invalid parameter offset for %s", desc[i].name);
+ log_err("invalid parameter offset for %s", desc[i].name);
} else {
value = *((u32 *)((u32)param +
desc[i].par_offset));
writel(value, ptr);
- debug("[0x%x] %s= 0x%08x\n",
- (u32)ptr, desc[i].name, value);
+ log_debug("[0x%x] %s= 0x%08x\n",
+ (u32)ptr, desc[i].name, value);
}
}
}
@@ -564,16 +566,16 @@
DDRPHYC_PGSR_RVERR |
DDRPHYC_PGSR_RVEIRR),
1000000);
- debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
- (u32)&phy->pgsr, pgsr, ret);
+ log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
+ (u32)&phy->pgsr, pgsr, ret);
}
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
{
pir |= DDRPHYC_PIR_INIT;
writel(pir, &phy->pir);
- debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
- (u32)&phy->pir, pir, readl(&phy->pir));
+ log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
+ (u32)&phy->pir, pir, readl(&phy->pir));
/* need to wait 10 configuration clock before start polling */
udelay(10);
@@ -603,7 +605,7 @@
panic("Timeout initialising DRAM : DDR->swstat = %x\n",
swstat);
- debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
+ log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
}
/* wait quasi dynamic register update */
@@ -634,7 +636,7 @@
if (ret)
panic("Timeout DRAM : DDR->stat = %x\n", stat);
- debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
+ log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
}
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
@@ -706,9 +708,9 @@
panic("ddr power init failed\n");
start:
- debug("name = %s\n", config->info.name);
- debug("speed = %d kHz\n", config->info.speed);
- debug("size = 0x%x\n", config->info.size);
+ log_debug("name = %s\n", config->info.name);
+ log_debug("speed = %d kHz\n", config->info.speed);
+ log_debug("size = 0x%x\n", config->info.size);
/*
* 1. Program the DWC_ddr_umctl2 registers
* 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
@@ -745,8 +747,8 @@
/* 1.5. initialize registers ddr_umctl2 */
/* Stop uMCTL2 before PHY is ready */
clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
- debug("[0x%08x] dfimisc = 0x%08x\n",
- (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
+ log_debug("[0x%08x] dfimisc = 0x%08x\n",
+ (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
set_reg(priv, REG_REG, &config->c_reg);
set_reg(priv, REG_TIMING, &config->c_timing);
@@ -809,9 +811,9 @@
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
if (config->p_cal_present) {
- debug("DDR DQS training skipped.\n");
+ log_debug("DDR DQS training skipped.\n");
} else {
- debug("DDR DQS training : ");
+ log_debug("DDR DQS training : ");
/* 8. Disable Auto refresh and power down by setting
* - RFSHCTL3.dis_au_refresh = 1
* - PWRCTL.powerdown_en = 0
diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c
index 5a5d067..e45a248 100644
--- a/drivers/ram/stm32mp1/stm32mp1_interactive.c
+++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c
@@ -3,6 +3,8 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <command.h>
#include <console.h>
@@ -404,7 +406,7 @@
#endif
}
- debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
+ log_debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
if (next_step < 0)
return false;
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index 0b6d20f..26f0b4f 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -12,6 +14,7 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include "stm32mp1_ddr.h"
static const char *const clkname[] = {
@@ -37,7 +40,7 @@
ret = clk_enable(&clk);
if (ret) {
- printf("error for %s : %d\n", clkname[idx], ret);
+ log_err("error for %s : %d\n", clkname[idx], ret);
return ret;
}
}
@@ -45,13 +48,13 @@
priv->clk = clk;
ddrphy_clk = clk_get_rate(&priv->clk);
- debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
- mem_speed, (u32)(ddrphy_clk / 1000));
+ log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000));
/* max 10% frequency delta */
ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
if (ddr_clk > (mem_speed * 100)) {
- pr_err("DDR expected freq %d kHz, current is %d kHz\n",
- mem_speed, (u32)(ddrphy_clk / 1000));
+ log_err("DDR expected freq %d kHz, current is %d kHz\n",
+ mem_speed, (u32)(ddrphy_clk / 1000));
return -EINVAL;
}
@@ -118,7 +121,7 @@
config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
config.info.name = ofnode_read_string(node, "st,mem-name");
if (!config.info.name) {
- debug("%s: no st,mem-name\n", __func__);
+ dev_dbg(dev, "no st,mem-name\n");
return -EINVAL;
}
printf("RAM: %s\n", config.info.name);
@@ -128,12 +131,12 @@
(void *)((u32)&config +
param[idx].offset),
param[idx].size);
- debug("%s: %s[0x%x] = %d\n", __func__,
- param[idx].name, param[idx].size, ret);
+ dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
+ param[idx].name, param[idx].size, ret);
if (ret &&
(ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
- pr_err("%s: Cannot read %s, error=%d\n",
- __func__, param[idx].name, ret);
+ dev_err(dev, "Cannot read %s, error=%d\n",
+ param[idx].name, ret);
return -EINVAL;
}
if (param[idx].present) {
@@ -153,7 +156,7 @@
ret = clk_get_by_name(dev, "axidcg", &axidcg);
if (ret) {
- debug("%s: Cannot found axidcg\n", __func__);
+ dev_dbg(dev, "%s: Cannot found axidcg\n", __func__);
return -EINVAL;
}
clk_disable(&axidcg); /* disable clock gating during init */
@@ -163,13 +166,13 @@
clk_enable(&axidcg); /* enable clock gating */
/* check size */
- debug("%s : get_ram_size(%x, %x)\n", __func__,
- (u32)priv->info.base, (u32)STM32_DDR_SIZE);
+ dev_dbg(dev, "get_ram_size(%x, %x)\n",
+ (u32)priv->info.base, (u32)STM32_DDR_SIZE);
priv->info.size = get_ram_size((long *)priv->info.base,
STM32_DDR_SIZE);
- debug("%s : %x\n", __func__, (u32)priv->info.size);
+ dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size);
/* check memory access for all memory */
if (config.info.size != priv->info.size) {
@@ -186,12 +189,11 @@
struct regmap *map;
int ret;
- debug("STM32MP1 DDR probe\n");
priv->dev = dev;
ret = regmap_init_mem(dev_ofnode(dev), &map);
if (ret)
- return ret;
+ return log_ret(ret);
priv->ctl = regmap_get_range(map, 0);
priv->phy = regmap_get_range(map, 1);
@@ -203,7 +205,9 @@
#if !defined(CONFIG_TFABOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
priv->info.size = 0;
- return stm32mp1_ddr_setup(dev);
+ ret = stm32mp1_ddr_setup(dev);
+
+ return log_ret(ret);
#else
ofnode node = stm32mp1_ddr_get_ofnode(dev);
priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c
index 952006a..1fcc7cf 100644
--- a/drivers/ram/stm32mp1/stm32mp1_tests.c
+++ b/drivers/ram/stm32mp1/stm32mp1_tests.c
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <console.h>
#include <init.h>
@@ -197,8 +200,8 @@
/* Read it back (immediately is okay for this test). */
read_value = readl(address);
- debug("%x: %x <=> %x\n",
- (u32)address, read_value, pattern);
+ log_debug("%x: %x <=> %x\n",
+ (u32)address, read_value, pattern);
if (read_value != pattern)
return pattern;
@@ -252,8 +255,8 @@
for (offset = 1; (offset & mask) != 0; offset <<= 1) {
read_value = readl(&address[offset]);
- debug("%x: %x <=> %x\n",
- (u32)&address[offset], read_value, pattern);
+ log_debug("%x: %x <=> %x\n",
+ (u32)&address[offset], read_value, pattern);
if (read_value != pattern)
return &address[offset];
}
@@ -363,8 +366,8 @@
data = readl(addr + 4 * i);
if (~(1 << i) != data) {
error |= 1 << i;
- debug("%x: error %x expected %x => error:%x\n",
- addr + 4 * i, data, ~(1 << i), error);
+ log_debug("%x: error %x expected %x => error:%x\n",
+ addr + 4 * i, data, ~(1 << i), error);
}
}
if (test_loop_end(&loop, nb_loop, 1000))
@@ -403,8 +406,8 @@
data = readl(addr + 4 * i);
if ((1 << i) != data) {
error |= 1 << i;
- debug("%x: error %x expected %x => error:%x\n",
- addr + 4 * i, data, (1 << i), error);
+ log_debug("%x: error %x expected %x => error:%x\n",
+ addr + 4 * i, data, (1 << i), error);
}
}
if (test_loop_end(&loop, nb_loop, 1000))
diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c
index a8d6892..c8cd7c3 100644
--- a/drivers/ram/stm32mp1/stm32mp1_tuning.c
+++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <console.h>
#include <clk.h>
@@ -227,8 +230,7 @@
index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
& DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
- pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
- __func__, addr, readl(addr), index);
+ log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index);
return index;
}
@@ -470,13 +472,13 @@
for (bit_i = 0; bit_i < 8; bit_i++) {
set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
index = DQ_unit_index(phy, byte, bit_i);
- pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
- byte, bit_i, deskew_delay[byte][bit_i],
- index, index - 3);
+ log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
+ byte, bit_i, deskew_delay[byte][bit_i],
+ index, index - 3);
printf("Byte %d, bit %d, DQ delay = %d",
byte, bit_i, deskew_delay[byte][bit_i]);
if (deskew_non_converge[byte][bit_i] == 1)
- pr_debug(" - not converged : still more skew");
+ log_debug(" - not converged : still more skew");
printf("\n");
}
}
@@ -536,7 +538,7 @@
/* Config the BIST block */
config_BIST(ctl, phy);
- pr_debug("BIST Config done.\n");
+ log_debug("BIST Config done.\n");
/* Train each byte */
for (datx8 = 0; datx8 < nb_bytes; datx8++) {
@@ -545,9 +547,9 @@
datx8 + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("\n======================\n");
- pr_debug("Start deskew byte %d .\n", datx8);
- pr_debug("======================\n");
+ log_debug("\n======================\n");
+ log_debug("Start deskew byte %d .\n", datx8);
+ log_debug("======================\n");
/* Enable Byte (DXNGCR, bit DXEN) */
setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
@@ -584,7 +586,7 @@
* Else, look for Pass init condition
*/
if (!success) {
- pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
+ log_debug("Fail at init condtion. Let's look for a good init condition.\n");
success = 0; /* init */
/* Make sure we start with a PASS condition before
* looking for a fail condition.
@@ -592,7 +594,7 @@
*/
/* escape if we find a PASS */
- pr_debug("increase Phase idx\n");
+ log_debug("increase Phase idx\n");
while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
DQS_phase_delay(phy, datx8, phase_idx);
BIST_test(phy, datx8, &result);
@@ -618,7 +620,7 @@
* we have hold violation, lets try reduce DQS_unit
* Delay
*/
- pr_debug("Still fail. Try decrease DQS Unit delay\n");
+ log_debug("Still fail. Try decrease DQS Unit delay\n");
phase_idx = 0;
dqs_unit_delay_index = 0;
@@ -665,9 +667,9 @@
return TEST_FAILED;
}
- pr_debug("there is a pass region for phase idx %d\n",
- phase_idx);
- pr_debug("Step1: Find the first failing condition\n");
+ log_debug("there is a pass region for phase idx %d\n",
+ phase_idx);
+ log_debug("Step1: Find the first failing condition\n");
/* Look for the first failing condition by PHASE stepping.
* This part of the algo can finish without converging.
*/
@@ -692,9 +694,9 @@
* stepping (minimal delay)
*/
if (!success) {
- pr_debug("Fail region (PHASE) found phase idx %d\n",
- phase_idx);
- pr_debug("Let's look for first success by DQS Unit steps\n");
+ log_debug("Fail region (PHASE) found phase idx %d\n",
+ phase_idx);
+ log_debug("Let's look for first success by DQS Unit steps\n");
/* This part, the algo always converge */
phase_idx--;
@@ -721,7 +723,7 @@
/*+1 to get back to current condition */
last_right_ok.unit = dqs_unit_delay_index + 1;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Found %d\n", dqs_unit_delay_index);
+ log_debug("Found %d\n", dqs_unit_delay_index);
} else {
/* the last OK condition is then with the
* previous phase_idx.
@@ -735,8 +737,8 @@
*/
last_right_ok.unit = 1;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Not Found : try previous phase %d\n",
- phase_idx - 1);
+ log_debug("Not Found : try previous phase %d\n",
+ phase_idx - 1);
DQS_phase_delay(phy, datx8, phase_idx - 1);
dqs_unit_delay_index = 0;
@@ -749,8 +751,8 @@
BIST_test(phy, datx8, &result);
success = result.test_result;
dqs_unit_delay_index++;
- pr_debug("dqs_unit_delay_index = %d, result = %d\n",
- dqs_unit_delay_index, success);
+ log_debug("dqs_unit_delay_index = %d, result = %d\n",
+ dqs_unit_delay_index, success);
}
if (!success) {
@@ -758,7 +760,7 @@
dqs_unit_delay_index - 1;
} else {
last_right_ok.unit = 0;
- pr_debug("ERROR: failed region not FOUND");
+ log_debug("ERROR: failed region not FOUND");
}
}
} else {
@@ -775,7 +777,7 @@
last_right_ok.phase = MAX_DQS_PHASE_IDX;
last_right_ok.unit = MAX_DQS_UNIT_IDX;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Can't find the a fail condition\n");
+ log_debug("Can't find the a fail condition\n");
}
/* step 2:
@@ -787,9 +789,9 @@
*/
printf("Byte %d, DQS unit = %d, phase = %d\n",
datx8, last_right_ok.unit, last_right_ok.phase);
- pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
- last_right_ok.unit, last_right_ok.phase,
- last_right_ok.bits_delay);
+ log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
+ last_right_ok.unit, last_right_ok.phase,
+ last_right_ok.bits_delay);
/* Restore the last_right_ok condtion. */
DQS_unit_delay(phy, datx8, last_right_ok.unit);
@@ -812,7 +814,7 @@
datx8 + 1, nb_bytes, error);
return error;
}
- pr_debug("deskewing bit %d:\n", bit_i);
+ log_debug("deskewing bit %d:\n", bit_i);
success = 1; /* init */
/* Set all DQDLYn to maximum value.
* Only bit_i will be down-delayed
@@ -855,10 +857,10 @@
* at one bit.
*/
fail_found = 1;
- pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
- bit_i, bit_i_delay_index + 1,
- datx8, bit_i,
- deskew_delay[datx8][bit_i]);
+ log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
+ bit_i, bit_i_delay_index + 1,
+ datx8, bit_i,
+ deskew_delay[datx8][bit_i]);
} else {
/* if we can find a success condition by
* back-delaying this bit, just set the delay
@@ -870,20 +872,20 @@
* in the report.
*/
deskew_non_converge[datx8][bit_i] = 1;
- pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
- bit_i, datx8, bit_i,
- deskew_delay[datx8][bit_i]);
+ log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
+ bit_i, datx8, bit_i,
+ deskew_delay[datx8][bit_i]);
}
}
- pr_debug("**********byte %d tuning complete************\n",
- datx8);
+ log_debug("**********byte %d tuning complete************\n",
+ datx8);
/* If we can't find any failure by back delaying DQ lines,
* hold the default values
*/
if (!fail_found) {
for (bit_i = 0; bit_i < 8; bit_i++)
deskew_delay[datx8][bit_i] = 0;
- pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
+ log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
}
apply_deskew_results(phy, datx8, deskew_delay,
@@ -986,7 +988,7 @@
dqs_unit_delay_index_pass = dqs_unit_delay_index;
success = 0;
- pr_debug("STEP0: Find Init delay\n");
+ log_debug("STEP0: Find Init delay\n");
/* STEP0: Find Init delay: a delay that put the system
* in a "Pass" condition then (TODO) update
* dqs_unit_delay_index_pass & phase_idx_pass
@@ -1035,7 +1037,7 @@
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
+ log_debug("STEP1: Find LEFT PHASE DQS Bound\n");
/* STEP1: Find LEFT PHASE DQS Bound */
while ((phase_idx >= 0) &&
(phase_idx <= MAX_DQS_PHASE_IDX) &&
@@ -1069,7 +1071,7 @@
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP2: Find UNIT left bound\n");
+ log_debug("STEP2: Find UNIT left bound\n");
/* STEP2: Find UNIT left bound */
while ((dqs_unit_delay_index >= 0) &&
!left_unit_bound_found) {
@@ -1097,7 +1099,7 @@
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP3: Find PHase right bound\n");
+ log_debug("STEP3: Find PHase right bound\n");
/* STEP3: Find PHase right bound, start with "pass"
* condition
*/
@@ -1135,7 +1137,7 @@
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP4: Find UNIT right bound\n");
+ log_debug("STEP4: Find UNIT right bound\n");
/* STEP4: Find UNIT right bound */
while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
!right_unit_bound_found) {
@@ -1174,12 +1176,12 @@
if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
eye_training_val[byte][1]++;
- pr_debug("** found phase : %d - %d & unit %d - %d\n",
- right_bound.phase, left_bound.phase,
- right_bound.unit, left_bound.unit);
- pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
- eye_training_val[byte][0],
- eye_training_val[byte][1]);
+ log_debug("** found phase : %d - %d & unit %d - %d\n",
+ right_bound.phase, left_bound.phase,
+ right_bound.unit, left_bound.unit);
+ log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
+ eye_training_val[byte][0],
+ eye_training_val[byte][1]);
} else {
/* PPPPPPPPPP, we're already good.
* Set nominal values.
@@ -1280,11 +1282,11 @@
* or pppppff or ffppppp
*/
if (left_bound_found || right_bound_found) {
- pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
- left_bound_found,
- right_bound_idx[0], left_bound_idx[0],
- right_bound_found,
- right_bound_idx[1], left_bound_idx[1]);
+ log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
+ left_bound_found,
+ right_bound_idx[0], left_bound_idx[0],
+ right_bound_found,
+ right_bound_idx[1], left_bound_idx[1]);
dqs_gate_values[byte][0] =
(right_bound_idx[0] + left_bound_idx[0]) / 2;
dqs_gate_values[byte][1] =
@@ -1319,14 +1321,14 @@
left_bound_idx[0];
}
}
- pr_debug("*******calculating mid region: system latency: %d phase: %d********\n",
- dqs_gate_values[byte][0],
- dqs_gate_values[byte][1]);
- pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
+ log_debug("*******calculating mid region: system latency: %d phase: %d********\n",
+ dqs_gate_values[byte][0],
+ dqs_gate_values[byte][1]);
+ log_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
}
} else {
/* if intermitant, restore defaut values */
- pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
+ log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
dqs_gate_values[byte][0] = 0;
dqs_gate_values[byte][1] = 2;
}
diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c
index ec7694d..4c5f248 100644
--- a/drivers/remoteproc/stm32_copro.c
+++ b/drivers/remoteproc/stm32_copro.c
@@ -2,7 +2,8 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
-#define pr_fmt(fmt) "%s: " fmt, __func__
+#define LOG_CATEGORY UCLASS_REMOTEPROC
+
#include <common.h>
#include <dm.h>
#include <errno.h>
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index b84c9da..daa2e47 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_RESET
+
#include <common.h>
#include <dm.h>
#include <errno.h>
@@ -12,6 +14,7 @@
#include <reset-uclass.h>
#include <stm32_rcc.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include <linux/bitops.h>
/* offset of register without set/clear management */
@@ -39,8 +42,9 @@
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
int offset = reset_ctl->id % BITS_PER_LONG;
- debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
- reset_ctl->id, bank, offset);
+
+ dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
+ reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
if (bank != RCC_MP_GCR_OFFSET)
@@ -59,8 +63,9 @@
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
int offset = reset_ctl->id % BITS_PER_LONG;
- debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
- reset_ctl->id, bank, offset);
+
+ dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
+ reset_ctl->id, bank, offset);
if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
if (bank != RCC_MP_GCR_OFFSET)
diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c
index f1d0ea9..1753283 100644
--- a/drivers/rtc/stm32_rtc.c
+++ b/drivers/rtc/stm32_rtc.c
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+
+#define LOG_CATEGORY UCLASS_RTC
+
#include <common.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 818c34c..f6cb708 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -4,6 +4,8 @@
* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_SERIAL
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -13,6 +15,7 @@
#include <watchdog.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
+#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include "serial_stm32.h"
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 4400857..75e5e84 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -7,6 +7,8 @@
* STM32 QSPI driver
*/
+#define LOG_CATEGORY UCLASS_SPI
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -136,7 +138,7 @@
!(sr & STM32_QSPI_SR_BUSY),
STM32_BUSY_TIMEOUT_US);
if (ret)
- pr_err("busy timeout (stat:%#x)\n", sr);
+ log_err("busy timeout (stat:%#x)\n", sr);
return ret;
}
@@ -154,9 +156,9 @@
sr & STM32_QSPI_SR_TCF,
STM32_QSPI_CMD_TIMEOUT_US);
if (ret) {
- pr_err("cmd timeout (stat:%#x)\n", sr);
+ log_err("cmd timeout (stat:%#x)\n", sr);
} else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
- pr_err("transfer error (stat:%#x)\n", sr);
+ log_err("transfer error (stat:%#x)\n", sr);
ret = -EIO;
}
@@ -198,7 +200,7 @@
sr & STM32_QSPI_SR_FTF,
STM32_QSPI_FIFO_TIMEOUT_US);
if (ret) {
- pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
+ log_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
return ret;
}
@@ -246,10 +248,10 @@
u8 mode = STM32_QSPI_CCR_IND_WRITE;
int timeout, ret;
- debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
- __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
- op->dummy.buswidth, op->data.buswidth,
- op->addr.val, op->data.nbytes);
+ dev_dbg(slave->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
+ op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
+ op->dummy.buswidth, op->data.buswidth,
+ op->addr.val, op->data.nbytes);
ret = _stm32_qspi_wait_for_not_busy(priv);
if (ret)
@@ -320,7 +322,7 @@
writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
if (ret || timeout)
- pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
+ dev_err(slave->dev, "ret:%d abort timeout:%d\n", ret, timeout);
return ret;
}
@@ -353,8 +355,8 @@
if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
return -EINVAL;
- debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
- __func__, priv->regs, priv->mm_base, priv->mm_size);
+ dev_dbg(bus, "regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
+ priv->regs, priv->mm_base, priv->mm_size);
ret = clk_get_by_index(bus, 0, &clk);
if (ret < 0)
@@ -475,8 +477,8 @@
STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
csht << STM32_QSPI_DCR_CSHT_SHIFT);
- debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
- (qspi_clk / (prescaler + 1)));
+ dev_dbg(bus, "regs=%p, speed=%d\n", priv->regs,
+ (qspi_clk / (prescaler + 1)));
return 0;
}
@@ -485,6 +487,7 @@
{
struct stm32_qspi_priv *priv = dev_get_priv(bus);
int ret;
+ const char *str_rx, *str_tx;
ret = _stm32_qspi_wait_for_not_busy(priv);
if (ret)
@@ -500,21 +503,22 @@
if (mode & SPI_CS_HIGH)
return -ENODEV;
- debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
-
if (mode & SPI_RX_QUAD)
- debug("quad, tx: ");
+ str_rx = "quad";
else if (mode & SPI_RX_DUAL)
- debug("dual, tx: ");
+ str_rx = "dual";
else
- debug("single, tx: ");
+ str_rx = "single";
if (mode & SPI_TX_QUAD)
- debug("quad\n");
+ str_tx = "quad";
else if (mode & SPI_TX_DUAL)
- debug("dual\n");
+ str_tx = "dual";
else
- debug("single\n");
+ str_tx = "single";
+
+ dev_dbg(bus, "regs=%p, mode=%d rx: %s, tx: %s\n",
+ priv->regs, mode, str_rx, str_tx);
return 0;
}
diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index 720103d..bd85140 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -4,6 +4,9 @@
*
* Driver for STMicroelectronics Serial peripheral interface (SPI)
*/
+
+#define LOG_CATEGORY UCLASS_SPI
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -138,7 +141,7 @@
}
}
- debug("%s: %d bytes left\n", __func__, priv->tx_len);
+ log_debug("%d bytes left\n", priv->tx_len);
}
static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
@@ -176,12 +179,12 @@
rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
}
- debug("%s: %d bytes left\n", __func__, priv->rx_len);
+ log_debug("%d bytes left\n", priv->rx_len);
}
static int stm32_spi_enable(struct stm32_spi_priv *priv)
{
- debug("%s\n", __func__);
+ log_debug("\n");
/* Enable the SPI hardware */
setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
@@ -191,7 +194,7 @@
static int stm32_spi_disable(struct stm32_spi_priv *priv)
{
- debug("%s\n", __func__);
+ log_debug("\n");
/* Disable the SPI hardware */
clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
@@ -204,7 +207,7 @@
struct udevice *bus = dev_get_parent(slave);
struct stm32_spi_priv *priv = dev_get_priv(bus);
- debug("%s\n", __func__);
+ dev_dbg(slave, "\n");
/* Enable the SPI hardware */
return stm32_spi_enable(priv);
@@ -215,7 +218,7 @@
struct udevice *bus = dev_get_parent(slave);
struct stm32_spi_priv *priv = dev_get_priv(bus);
- debug("%s\n", __func__);
+ dev_dbg(slave, "\n");
/* Disable the SPI hardware */
return stm32_spi_disable(priv);
@@ -227,7 +230,7 @@
u32 cr1, sr;
int ret;
- debug("%s\n", __func__);
+ dev_dbg(dev, "\n");
cr1 = readl(priv->base + STM32_SPI_CR1);
@@ -255,7 +258,7 @@
{
struct stm32_spi_priv *priv = dev_get_priv(dev);
- debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
+ dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
if (cs >= MAX_CS_COUNT)
return -ENODEV;
@@ -274,7 +277,7 @@
struct stm32_spi_priv *priv = dev_get_priv(bus);
u32 cfg2_clrb = 0, cfg2_setb = 0;
- debug("%s: mode=%d\n", __func__, mode);
+ dev_dbg(bus, "mode=%d\n", mode);
if (mode & SPI_CPOL)
cfg2_setb |= SPI_CFG2_CPOL;
@@ -330,7 +333,7 @@
u32 mbrdiv;
long div;
- debug("%s: hz=%d\n", __func__, hz);
+ dev_dbg(bus, "hz=%d\n", hz);
if (priv->cur_hz == hz)
return 0;
@@ -404,8 +407,8 @@
stm32_spi_enable(priv);
}
- debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
- priv->tx_len, priv->rx_len);
+ dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n",
+ priv->tx_len, priv->rx_len);
slave_plat = dev_get_parent_plat(slave);
if (flags & SPI_XFER_BEGIN)
@@ -477,7 +480,7 @@
stm32_spi_disable(priv);
- debug("%s %d x 8-bit fifo size\n", __func__, count);
+ dev_dbg(dev, "%d x 8-bit fifo size\n", count);
return count;
}
@@ -522,7 +525,7 @@
ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
ARRAY_SIZE(priv->cs_gpios), 0);
if (ret < 0) {
- pr_err("Can't get %s cs gpios: %d", dev->name, ret);
+ dev_err(dev, "Can't get cs gpios: %d", ret);
goto reset_err;
}
diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c
index 215334f..e34f520 100644
--- a/drivers/timer/stm32_timer.c
+++ b/drivers/timer/stm32_timer.c
@@ -4,6 +4,8 @@
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_TIMER
+
#include <common.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index a3f8eeb..d39d9b2 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -449,6 +449,15 @@
The reset pin of SSD2828 chip. This takes a string in the format
understood by 'name_to_gpio' function, e.g. PH1 for pin 1 of port H.
+config VIDEO_LCD_TDO_TL070WSH30
+ bool "TDO TL070WSH30 DSI LCD panel support"
+ depends on DM_VIDEO
+ select VIDEO_MIPI_DSI
+ default n
+ help
+ Say Y here if you want to enable support for TDO TL070WSH30
+ 1024x600 DSI video mode panel.
+
config VIDEO_LCD_HITACHI_TX18D42VM
bool "Hitachi tx18d42vm LVDS LCD panel support"
depends on VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 76e3914..494e414 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -56,6 +56,7 @@
obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
+obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-${CONFIG_VIDEO_MESON} += meson/
obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
index 266623b..8891ca4 100644
--- a/drivers/video/stm32/stm32_dsi.c
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -8,6 +8,8 @@
* drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.
*/
+#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -133,7 +135,7 @@
case MIPI_DSI_FMT_RGB565:
return DSI_RGB565_CONF1;
default:
- pr_err("MIPI color invalid, so we use rgb888\n");
+ log_err("MIPI color invalid, so we use rgb888\n");
}
return DSI_RGB888;
}
@@ -213,14 +215,14 @@
u32 val;
int ret;
- debug("Initialize DSI physical layer\n");
+ dev_dbg(dev, "Initialize DSI physical layer\n");
/* Enable the regulator */
dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
TIMEOUT_US);
if (ret) {
- debug("!TIMEOUT! waiting REGU\n");
+ dev_dbg(dev, "!TIMEOUT! waiting REGU\n");
return ret;
}
@@ -229,7 +231,7 @@
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
TIMEOUT_US);
if (ret) {
- debug("!TIMEOUT! waiting PLL\n");
+ dev_dbg(dev, "!TIMEOUT! waiting PLL\n");
return ret;
}
@@ -242,8 +244,8 @@
struct udevice *dev = device->dev;
struct stm32_dsi_priv *dsi = dev_get_priv(dev);
- debug("Set mode %p enable %ld\n", dsi,
- mode_flags & MIPI_DSI_MODE_VIDEO);
+ dev_dbg(dev, "Set mode %p enable %ld\n", dsi,
+ mode_flags & MIPI_DSI_MODE_VIDEO);
if (!dsi)
return;
@@ -325,8 +327,8 @@
*lane_mbps = pll_out_khz / 1000;
- debug("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
- pll_in_khz, pll_out_khz, *lane_mbps);
+ dev_dbg(dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
+ pll_in_khz, pll_out_khz, *lane_mbps);
return 0;
}
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index dc10b8c..f55a394 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -5,6 +5,8 @@
* Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
*/
+#define LOG_CATEGORY UCLASS_VIDEO
+
#include <common.h>
#include <clk.h>
#include <display.h>
@@ -176,13 +178,13 @@
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
- pr_warn("%s: warning %dbpp not supported yet, %dbpp instead\n",
- __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+ log_warning("warning %dbpp not supported yet, %dbpp instead\n",
+ VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
- debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
+ log_debug("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
return (u32)pf;
}
@@ -249,7 +251,7 @@
/* Signal polarities */
val = 0;
- debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+ log_debug("timing->flags 0x%08x\n", timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@@ -379,8 +381,8 @@
dev_warn(dev, "fail to set pixel clock %d hz\n",
timings.pixelclock.typ);
- debug("%s: Set pixel clock req %d hz get %ld hz\n", __func__,
- timings.pixelclock.typ, clk_get_rate(&pclk));
+ dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
+ timings.pixelclock.typ, clk_get_rate(&pclk));
ret = reset_get_by_index(dev, 0, &rst);
if (ret) {
@@ -394,12 +396,13 @@
if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
if (ret)
- debug("No video bridge, or no backlight on bridge\n");
+ dev_dbg(dev,
+ "No video bridge, or no backlight on bridge\n");
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
- dev_err(dev, "fail to attach bridge\n");
+ dev_err(bridge, "fail to attach bridge\n");
return ret;
}
}
@@ -414,12 +417,12 @@
priv->crop_h = timings.vactive.typ;
priv->alpha = 0xFF;
- debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__,
- timings.hactive.typ, timings.vactive.typ,
- VNBITS(priv->l2bpp), uc_plat->base);
- debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__,
- priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
- priv->bg_col_argb, priv->alpha);
+ dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
+ timings.hactive.typ, timings.vactive.typ,
+ VNBITS(priv->l2bpp), uc_plat->base);
+ dev_dbg(dev, "crop %d,%d %dx%d bg 0x%08x alpha %d\n",
+ priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
+ priv->bg_col_argb, priv->alpha);
/* Configure & start LTDC */
stm32_ltdc_set_mode(priv, &timings);
@@ -457,7 +460,7 @@
uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
CONFIG_VIDEO_STM32_MAX_YRES *
(CONFIG_VIDEO_STM32_MAX_BPP >> 3);
- debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size);
+ dev_dbg(dev, "frame buffer max size %d bytes\n", uc_plat->size);
return 0;
}
diff --git a/drivers/video/tdo-tl070wsh30.c b/drivers/video/tdo-tl070wsh30.c
new file mode 100644
index 0000000..ae9d11f
--- /dev/null
+++ b/drivers/video/tdo-tl070wsh30.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+#include <common.h>
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+
+struct tl070wsh30_panel_priv {
+ struct udevice *reg;
+ struct udevice *backlight;
+ struct gpio_desc reset;
+};
+
+static const struct display_timing default_timing = {
+ .pixelclock.typ = 47250000,
+ .hactive.typ = 1024,
+ .hfront_porch.typ = 46,
+ .hback_porch.typ = 100,
+ .hsync_len.typ = 80,
+ .vactive.typ = 600,
+ .vfront_porch.typ = 5,
+ .vback_porch.typ = 20,
+ .vsync_len.typ = 5,
+ .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH,
+};
+
+static int tl070wsh30_panel_enable_backlight(struct udevice *dev)
+{
+ struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ struct mipi_dsi_device *device = plat->device;
+ struct tl070wsh30_panel_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = mipi_dsi_attach(device);
+ if (ret < 0)
+ return ret;
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(device);
+ if (ret)
+ return ret;
+
+ mdelay(200);
+
+ ret = mipi_dsi_dcs_set_display_on(device);
+ if (ret)
+ return ret;
+
+ mdelay(20);
+
+ ret = backlight_enable(priv->backlight);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int tl070wsh30_panel_get_display_timing(struct udevice *dev,
+ struct display_timing *timings)
+{
+ memcpy(timings, &default_timing, sizeof(*timings));
+
+ return 0;
+}
+
+static int tl070wsh30_panel_ofdata_to_platdata(struct udevice *dev)
+{
+ struct tl070wsh30_panel_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+ ret = device_get_supply_regulator(dev, "power-supply",
+ &priv->reg);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "Warning: cannot get power supply\n");
+ return ret;
+ }
+ }
+
+ ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
+ GPIOD_IS_OUT);
+ if (ret) {
+ dev_err(dev, "Warning: cannot get reset GPIO\n");
+ if (ret != -ENOENT)
+ return ret;
+ }
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", &priv->backlight);
+ if (ret) {
+ dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tl070wsh30_panel_probe(struct udevice *dev)
+{
+ struct tl070wsh30_panel_priv *priv = dev_get_priv(dev);
+ struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+ int ret;
+
+ if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
+ ret = regulator_set_enable(priv->reg, true);
+ if (ret)
+ return ret;
+ }
+
+ mdelay(10);
+
+ /* reset panel */
+ dm_gpio_set_value(&priv->reset, true);
+
+ mdelay(10);
+
+ dm_gpio_set_value(&priv->reset, false);
+
+ /* fill characteristics of DSI data link */
+ plat->lanes = 4;
+ plat->format = MIPI_DSI_FMT_RGB888;
+ plat->mode_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_LPM;
+
+ return 0;
+}
+
+static const struct panel_ops tl070wsh30_panel_ops = {
+ .enable_backlight = tl070wsh30_panel_enable_backlight,
+ .get_display_timing = tl070wsh30_panel_get_display_timing,
+};
+
+static const struct udevice_id tl070wsh30_panel_ids[] = {
+ { .compatible = "tdo,tl070wsh30" },
+ { }
+};
+
+U_BOOT_DRIVER(tl070wsh30_panel) = {
+ .name = "tl070wsh30_panel",
+ .id = UCLASS_PANEL,
+ .of_match = tl070wsh30_panel_ids,
+ .ops = &tl070wsh30_panel_ops,
+ .ofdata_to_platdata = tl070wsh30_panel_ofdata_to_platdata,
+ .probe = tl070wsh30_panel_probe,
+ .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
+ .priv_auto_alloc_size = sizeof(struct tl070wsh30_panel_priv),
+};
diff --git a/drivers/watchdog/stm32mp_wdt.c b/drivers/watchdog/stm32mp_wdt.c
index 53586fd..4be616c 100644
--- a/drivers/watchdog/stm32mp_wdt.c
+++ b/drivers/watchdog/stm32mp_wdt.c
@@ -3,6 +3,8 @@
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_WDT
+
#include <common.h>
#include <clk.h>
#include <dm.h>
@@ -10,6 +12,7 @@
#include <syscon.h>
#include <wdt.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
@@ -77,7 +80,7 @@
val & (SR_PVU | SR_RVU), CONFIG_SYS_HZ);
if (ret < 0) {
- pr_err("Updating IWDG registers timeout");
+ dev_err(dev, "Updating IWDG registers timeout");
return -ETIMEDOUT;
}
@@ -90,7 +93,7 @@
struct clk clk;
int ret;
- debug("IWDG init\n");
+ dev_dbg(dev, "IWDG init\n");
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
@@ -112,7 +115,7 @@
priv->wdt_clk_rate = clk_get_rate(&clk);
- debug("IWDG init done\n");
+ dev_dbg(dev, "IWDG init done\n");
return 0;
}
diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h
new file mode 100644
index 0000000..e524388
--- /dev/null
+++ b/include/dt-bindings/power/meson-axg-power.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_AXG_POWER_H
+#define _DT_BINDINGS_MESON_AXG_POWER_H
+
+#define PWRC_AXG_VPU_ID 0
+#define PWRC_AXG_ETHERNET_MEM_ID 1
+#define PWRC_AXG_AUDIO_ID 2
+
+#endif
diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h
new file mode 100644
index 0000000..1262dac
--- /dev/null
+++ b/include/dt-bindings/power/meson-gxbb-power.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H
+#define _DT_BINDINGS_MESON_GXBB_POWER_H
+
+#define PWRC_GXBB_VPU_ID 0
+#define PWRC_GXBB_ETHERNET_MEM_ID 1
+
+#endif