armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 8f65d7e..f92c23d 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -17,6 +17,8 @@
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */