armv7: add cacheline sizes where missing
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 02fdcdc..6a4868c 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -14,6 +14,11 @@
#ifndef __CONFIG_TI_OMAP3_COMMON_H__
#define __CONFIG_TI_OMAP3_COMMON_H__
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>