| commit | 379c5145ef8f3adbcfeb0a47503838627959cb67 | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Mon Oct 08 07:44:16 2012 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Mon Oct 22 14:31:20 2012 -0500 |
| tree | d3125ad2d838363ae8b4eb617a38620f19c6e12c | |
| parent | d1001e3f0ce0059a55a870c42bac8aba2e4befec [diff] |
powerpc/corenet2: fix mismatch DDR sync bit from RCW Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only async mode is supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>