rockchip: clk: Support setting ACLK
Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index ed97e87..d15504c 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -691,6 +691,13 @@
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
switch (clk->id) {
+ case PLL_APLL:
+ /* We only support a fixed rate here */
+ if (rate != 1800000000)
+ return -EINVAL;
+ rk3288_clk_configure_cpu(priv->cru, priv->grf);
+ new_rate = rate;
+ break;
case CLK_DDR:
new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
break;