| commit | 3b00fab616b1150da745bbb36f6644842a24624f | [log] [tgz] |
|---|---|---|
| author | Samuel Holland <samuel@sholland.org> | Tue Oct 31 00:35:41 2023 -0500 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Thu Nov 02 15:15:46 2023 +0800 |
| tree | ec370646297026107f4d3d5865648546945e7e05 | |
| parent | a6a77e47343d0b511136b76da0c853304a3f1423 [diff] |
riscv: Align the trap handler to 64 bytes This is required on CPUs which always operate in CLIC mode, such as the T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the trap vector base address held in mtvec is constrained to be aligned on a 64-byte or larger power-of-two boundary." Reported-by: Madushan Nishantha <jlmadushan@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>