PXA: pxa-regs.h cleanup
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c
index 84ec38e..8aa7067 100644
--- a/board/colibri_pxa270/colibri_pxa270.c
+++ b/board/colibri_pxa270/colibri_pxa270.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -65,28 +66,30 @@
#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (UHCHR & UHCHR_FSBIR);
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(0x200);
- UHCRHDA |= 0x100;
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
- UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
@@ -98,14 +101,14 @@
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index 21eb655..c4a93f9 100644
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -28,6 +28,7 @@
#include <asm/arch/pxa-regs.h>
#include <common.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -92,8 +93,8 @@
int shift = led * 2;
unsigned long mask = 0x3 << shift;
- CRADLE_LED_CLR_REG = mask; /* clear bits */
- CRADLE_LED_SET_REG = (color << shift); /* set bits */
+ writel(mask, GPCR2); /* clear bits */
+ writel((color << shift), GPSR2); /* set bits */
udelay (5000);
}
diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S
index 6b5cfb9..39964b6 100644
--- a/board/cradle/lowlevel_init.S
+++ b/board/cradle/lowlevel_init.S
@@ -34,10 +34,10 @@
.endm
.macro SET_LED val
- ldr r6, =CRADLE_LED_CLR_REG
+ ldr r6, =GPCR2
ldr r7, =0
str r7, [r6]
- ldr r6, =CRADLE_LED_SET_REG
+ ldr r6, =GPSR2
ldr r7, =\val
str r7, [r6]
.endm
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index 0a6c13d..6eed9ad 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -26,6 +26,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -108,23 +109,23 @@
switch(led) {
case 0: if (state==1) {
- GPCR0 |= CSB226_USER_LED0;
+ writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED0;
+ writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
}
break;
case 1: if (state==1) {
- GPCR0 |= CSB226_USER_LED1;
+ writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED1;
+ writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
}
break;
case 2: if (state==1) {
- GPCR0 |= CSB226_USER_LED2;
+ writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED2;
+ writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
}
break;
}
diff --git a/board/delta/delta.c b/board/delta/delta.c
index 68c39d2..df23076 100644
--- a/board/delta/delta.c
+++ b/board/delta/delta.c
@@ -28,6 +28,7 @@
#include <malloc.h>
#include <command.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -110,7 +111,7 @@
static void get_pressed_keys(uchar *s)
{
unsigned long val;
- val = GPLR3;
+ val = readl(GPLR3);
if(val & (1<<31))
*s++ = KEYBD_KP_DKIN0;
@@ -124,18 +125,18 @@
static void keys_init()
{
- CKENB |= CKENB_7_GPIO;
+ writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
udelay(100);
/* Configure GPIOs */
- GPIO127 = 0xa840; /* KP_DKIN0 */
- GPIO114 = 0xa840; /* KP_DKIN1 */
- GPIO125 = 0xa840; /* KP_DKIN2 */
- GPIO118 = 0xa840; /* KP_DKIN5 */
+ writel(0xa840, GPIO127); /* KP_DKIN0 */
+ writel(0xa840, GPIO114); /* KP_DKIN1 */
+ writel(0xa840, GPIO125); /* KP_DKIN2 */
+ writel(0xa840, GPIO118); /* KP_DKIN5 */
/* Configure GPIOs as inputs */
- GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22);
- GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22);
+ writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
+ writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
udelay(100);
}
@@ -283,11 +284,11 @@
void i2c_init_board()
{
- CKENB |= (CKENB_4_I2C);
+ writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
/* setup I2C GPIO's */
- GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */
- GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */
+ writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */
+ writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */
}
/* initialize the DA9030 Power Controller */
@@ -295,20 +296,20 @@
{
uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
- CKENB |= CKENB_7_GPIO;
+ writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
udelay(100);
/* Rising Edge on EXTON to reset DA9030 */
- GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */
- GPDR0 |= (1<<17); /* GPIO17 is output */
- GSDR0 = (1<<17);
- GPCR0 = (1<<17); /* drive GPIO17 low */
- GPSR0 = (1<<17); /* drive GPIO17 high */
+ writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */
+ writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */
+ writel((1<<17), GSDR0);
+ writel((1<<17), GPCR0); /* drive GPIO17 low */
+ writel((1<<17), GPSR0); /* drive GPIO17 high */
#if CONFIG_SYS_DA9030_EXTON_DELAY
udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */
#endif
- GPCR0 = (1<<17); /* drive GPIO17 low */
+ writel((1<<17), GPCR0); /* drive GPIO17 low */
/* reset the watchdog and go active (0xec) */
val = (SYS_CONTROL_A_HWRES_ENABLE |
diff --git a/board/delta/nand.c b/board/delta/nand.c
index 85a6ba2..119a587 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -26,6 +26,7 @@
#include <nand.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
#ifdef CONFIG_SYS_DFC_DEBUG1
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
@@ -95,7 +96,7 @@
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- NDDB = *long_buf;
+ writel(*long_buf, NDDB);
}
}
if(rest) {
@@ -120,7 +121,7 @@
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- *long_buf = NDDB;
+ *long_buf = readl(NDDB);
}
}
@@ -166,8 +167,8 @@
unsigned long dummy;
if(bytes_read < 0) {
- read_buf = NDDB;
- dummy = NDDB;
+ read_buf = readl(NDDB);
+ dummy = readl(NDDB);
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@@ -181,7 +182,7 @@
/* calculate delta between OSCR values start and now */
static unsigned long get_delta(unsigned long start)
{
- unsigned long cur = OSCR;
+ unsigned long cur = readl(OSCR);
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
@@ -192,7 +193,7 @@
/* delay function, this doesn't belong here */
static void wait_us(unsigned long us)
{
- unsigned long start = OSCR;
+ unsigned long start = readl(OSCR);
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
@@ -202,14 +203,14 @@
static void dfc_clear_nddb(void)
{
- NDCR &= ~NDCR_ND_RUN;
+ writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
static unsigned long dfc_wait_event(unsigned long event)
{
- unsigned long ndsr, timeout, start = OSCR;
+ unsigned long ndsr, timeout, start = readl(OSCR);
if(!event)
return 0xff000000;
@@ -221,9 +222,9 @@
* OSCR_CLK_FREQ, 1000);
while(1) {
- ndsr = NDSR;
+ ndsr = readl(NDSR);
if(ndsr & event) {
- NDSR |= event;
+ writel(readl(NDSR) | event, NDSR);
break;
}
if(get_delta(start) > timeout) {
@@ -243,11 +244,11 @@
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
- NDSR = 0xFFF;
+ writel(0xfff, NDSR);
/* set NDCR[NDRUN] */
- if(!(NDCR & NDCR_ND_RUN))
- NDCR |= NDCR_ND_RUN;
+ if (!(readl(NDCR) & NDCR_ND_RUN))
+ writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
status = dfc_wait_event(NDSR_WRCMDREQ);
@@ -357,9 +358,9 @@
}
write_cmd:
- NDCB0 = ndcb0;
- NDCB0 = ndcb1;
- NDCB0 = ndcb2;
+ writel(ndcb0, NDCB0);
+ writel(ndcb1, NDCB0);
+ writel(ndcb2, NDCB0);
/* wait_event: */
dfc_wait_event(event);
@@ -372,36 +373,36 @@
DFC_DEBUG2("Setting up DFC GPIO's.\n");
/* no idea what is done here, see zylonite.c */
- GPIO4 = 0x1;
+ writel(0x1, GPIO4);
- DF_ALE_WE1 = 0x00000001;
- DF_ALE_WE2 = 0x00000001;
- DF_nCS0 = 0x00000001;
- DF_nCS1 = 0x00000001;
- DF_nWE = 0x00000001;
- DF_nRE = 0x00000001;
- DF_IO0 = 0x00000001;
- DF_IO8 = 0x00000001;
- DF_IO1 = 0x00000001;
- DF_IO9 = 0x00000001;
- DF_IO2 = 0x00000001;
- DF_IO10 = 0x00000001;
- DF_IO3 = 0x00000001;
- DF_IO11 = 0x00000001;
- DF_IO4 = 0x00000001;
- DF_IO12 = 0x00000001;
- DF_IO5 = 0x00000001;
- DF_IO13 = 0x00000001;
- DF_IO6 = 0x00000001;
- DF_IO14 = 0x00000001;
- DF_IO7 = 0x00000001;
- DF_IO15 = 0x00000001;
+ writel(0x00000001, DF_ALE_nWE1);
+ writel(0x00000001, DF_ALE_nWE2);
+ writel(0x00000001, DF_nCS0);
+ writel(0x00000001, DF_nCS1);
+ writel(0x00000001, DF_nWE);
+ writel(0x00000001, DF_nRE);
+ writel(0x00000001, DF_IO0);
+ writel(0x00000001, DF_IO8);
+ writel(0x00000001, DF_IO1);
+ writel(0x00000001, DF_IO9);
+ writel(0x00000001, DF_IO2);
+ writel(0x00000001, DF_IO10);
+ writel(0x00000001, DF_IO3);
+ writel(0x00000001, DF_IO11);
+ writel(0x00000001, DF_IO4);
+ writel(0x00000001, DF_IO12);
+ writel(0x00000001, DF_IO5);
+ writel(0x00000001, DF_IO13);
+ writel(0x00000001, DF_IO6);
+ writel(0x00000001, DF_IO14);
+ writel(0x00000001, DF_IO7);
+ writel(0x00000001, DF_IO15);
- DF_nWE = 0x1901;
- DF_nRE = 0x1901;
- DF_CLE_NOE = 0x1900;
- DF_ALE_WE1 = 0x1901;
- DF_INT_RnB = 0x1900;
+ writel(0x1901, DF_nWE);
+ writel(0x1901, DF_nRE);
+ writel(0x1900, DF_CLE_nOE);
+ writel(0x1901, DF_ALE_nWE1);
+ writel(0x1900, DF_INT_RnB);
}
/*
@@ -430,7 +431,7 @@
dfc_gpio_init();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
- CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+ writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
#undef CONFIG_SYS_TIMING_TIGHT
#ifndef CONFIG_SYS_TIMING_TIGHT
@@ -485,17 +486,19 @@
tRP_high = 0;
}
- NDTR0CS0 = (tCH << 19) |
+ writel((tCH << 19) |
(tCS << 16) |
(tWH << 11) |
(tWP << 8) |
(tRP_high << 6) |
(tRH << 3) |
- (tRP << 0);
+ (tRP << 0),
+ NDTR0CS0);
- NDTR1CS0 = (tR << 16) |
+ writel((tR << 16) |
(tWHR << 4) |
- (tAR << 0);
+ (tAR << 0),
+ NDTR1CS0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
@@ -512,7 +515,7 @@
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
- NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ writel(NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
(2 << 16) | /* read id count = 7 ???? mk@tbd */
@@ -528,7 +531,8 @@
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM); /* write command request ir masked */
+ NDCR_WRCMDREQM, /* write command request ir masked */
+ NDCR);
/* wait 10 us due to cmd buffer clear reset */
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index 3412f10..2c51125 100644
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -27,6 +27,7 @@
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -48,20 +49,21 @@
/* disable I2C controller first, otherwhise it thinks we want to */
/* talk to the slave port... */
- icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
+ icr = readl(ICR);
+ writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
/* set gpio pin low _before_ we change direction to output */
- GPCR(70) = GPIO_bit(70);
+ writel(GPIO_bit(70), GPCR(70));
/* now toggle between output=low and high-impedance */
for (i = 0; i < 20; i++) {
- GPDR(70) |= GPIO_bit(70); /* output */
+ writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */
udelay(10);
- GPDR(70) &= ~GPIO_bit(70); /* input */
+ writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */
udelay(10);
}
- ICR = icr;
+ writel(icr, ICR);
return 0;
}
@@ -76,7 +78,7 @@
char *str;
/* determine if the software update key is pressed during startup */
- if (GPLR0 & 0x00000800) {
+ if (readl(GPLR0) & 0x00000800) {
printf("using bootcmd_normal (sw-update button not pressed)\n");
str = getenv("bootcmd_normal");
} else {
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index a54a95d..4ab8bd4 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -33,6 +33,7 @@
#include <common.h>
#include <netdev.h>
#include <command.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -56,14 +57,14 @@
/* set PWM for LCD */
/* a value that works is 60Hz, 77% duty cycle */
- CKEN |= CKEN0_PWM0;
- PWM_CTRL0 = 0x3f;
- PWM_PERVAL0 = 0x3ff;
- PWM_PWDUTY0 = 792;
+ writel(readl(CKEN) | CKEN0_PWM0, CKEN);
+ writel(0x3f, PWM_CTRL0);
+ writel(0x3ff, PWM_PERVAL0);
+ writel(792, PWM_PWDUTY0);
/* clear reset to AC97 codec */
- CKEN |= CKEN2_AC97;
- GCR = GCR_COLD_RST;
+ writel(readl(CKEN) | CKEN2_AC97, CKEN);
+ writel(GCR_COLD_RST, GCR);
/* enable LCD backlight */
/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
@@ -102,11 +103,11 @@
void delay_c(void)
{
/* reset OSCR to 0 */
- OSCR = 0;
- while(OSCR > 0x10000)
+ writel(0, OSCR);
+ while (readl(OSCR) > 0x10000)
;
- while(OSCR < 0xd4000)
+ while (readl(OSCR) < 0xd4000)
;
}
@@ -114,12 +115,12 @@
{
int led_bit = (1<<10);
- GPDR0 = led_bit;
- GPCR0 = led_bit;
+ writel(led_bit, GPDR0);
+ writel(led_bit, GPCR0);
delay_c();
- GPSR0 = led_bit;
+ writel(led_bit, GPSR0);
delay_c();
- GPCR0 = led_bit;
+ writel(led_bit, GPCR0);
}
int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 8c11456..7fac73d 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -34,6 +34,7 @@
#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -57,25 +58,27 @@
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(RH_A_NPS);
- UHCRHDA |= RH_A_PSM;
+ writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+ writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
return 0;
}
@@ -87,14 +90,14 @@
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
index 18e47e2..f792298 100644
--- a/board/vpac270/vpac270.c
+++ b/board/vpac270/vpac270.c
@@ -31,6 +31,8 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -75,28 +77,31 @@
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(0x200);
- UHCRHDA |= 0x100;
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
- UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
@@ -108,14 +113,14 @@
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c
index fe4b6a9..6e41ea6 100644
--- a/board/wepep250/wepep250.c
+++ b/board/wepep250/wepep250.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,13 +34,13 @@
* Setup GPIO stuff to get serial working
*/
#if defined( CONFIG_FFUART )
- GPDR1 = 0x80;
- GAFR1_L = 0x8010;
+ writel(0x80, GPDR1);
+ writel(0x8010, GAFR1_L);
#elif defined( CONFIG_BTUART )
- GPDR1 = 0x800;
- GAFR1_L = 0x900000;
+ writel(0x800, GPDR1);
+ writel(0x900000, GAFR1_L);
#endif
- PSSR = 0x20;
+ writel(0x20, PSSR);
return 0;
}
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
index 14d1d76..f7edc4c 100644
--- a/board/zipitz2/zipitz2.c
+++ b/board/zipitz2/zipitz2.c
@@ -28,6 +28,7 @@
#include <serial.h>
#include <asm/arch/hardware.h>
#include <spi.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -129,24 +130,24 @@
{
/* GPIO 13 */
if (set)
- GPSR0 = (1 << 13);
+ writel((1 << 13), GPSR0);
else
- GPCR0 = (1 << 13);
+ writel((1 << 13), GPCR0);
}
void zipitz2_spi_scl(int set)
{
/* GPIO 22 */
if (set)
- GPCR0 = (1 << 22);
+ writel((1 << 22), GPCR0);
else
- GPSR0 = (1 << 22);
+ writel((1 << 22), GPSR0);
}
unsigned char zipitz2_spi_read(void)
{
/* GPIO 40 */
- return !!(GPLR1 & (1 << 8));
+ return !!(readl(GPLR1) & (1 << 8));
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -158,13 +159,13 @@
void spi_cs_activate(struct spi_slave *slave)
{
/* GPIO 88 low */
- GPCR2 = (1 << 24);
+ writel((1 << 24), GPCR2);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* GPIO 88 high */
- GPSR2 = (1 << 24);
+ writel((1 << 24), GPSR2);
}
@@ -176,20 +177,20 @@
unsigned char dummy[3] = { 0, 0, 0 };
/* PWM2 AF */
- GAFR0_L |= 0x00800000;
+ writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
/* Enable clock to all PWM */
- CKEN |= 0x3;
+ writel(readl(CKEN) | 0x3, CKEN);
/* Configure PWM2 */
- PWM_CTRL2 = 0x4f;
- PWM_PWDUTY2 = 0x2ff;
- PWM_PERVAL2 = 792;
+ writel(0x4f, PWM_CTRL2);
+ writel(0x2ff, PWM_PWDUTY2);
+ writel(792, PWM_PERVAL2);
/* Toggle the reset pin to reset the LCD */
- GPSR0 = (1 << 19);
+ writel((1 << 19), GPSR0);
udelay(100000);
- GPCR0 = (1 << 19);
+ writel((1 << 19), GPCR0);
udelay(20000);
- GPSR0 = (1 << 19);
+ writel((1 << 19), GPSR0);
udelay(20000);
/* Program the LCD init sequence */
@@ -208,6 +209,6 @@
udelay(lcd_data[i].mdelay * 1000);
}
- GPSR0 = (1 << 11);
+ writel((1 << 11), GPSR0);
}
#endif
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index 7cad1ac..71d18a6 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -21,6 +21,7 @@
*/
#include <common.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NAND)
@@ -95,7 +96,7 @@
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- NDDB = *long_buf;
+ writel(*long_buf, NDDB);
}
}
if(rest) {
@@ -125,7 +126,7 @@
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- *long_buf = NDDB;
+ *long_buf = readl(NDDB);
}
}
@@ -171,8 +172,8 @@
unsigned long dummy;
if(bytes_read < 0) {
- read_buf = NDDB;
- dummy = NDDB;
+ read_buf = readl(NDDB);
+ dummy = readl(NDDB);
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@@ -186,7 +187,7 @@
/* calculate delta between OSCR values start and now */
static unsigned long get_delta(unsigned long start)
{
- unsigned long cur = OSCR;
+ unsigned long cur = readl(OSCR);
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
@@ -197,7 +198,7 @@
/* delay function, this doesn't belong here */
static void wait_us(unsigned long us)
{
- unsigned long start = OSCR;
+ unsigned long start = readl(OSCR);
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
@@ -207,14 +208,14 @@
static void dfc_clear_nddb(void)
{
- NDCR &= ~NDCR_ND_RUN;
+ writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
static unsigned long dfc_wait_event(unsigned long event)
{
- unsigned long ndsr, timeout, start = OSCR;
+ unsigned long ndsr, timeout, start = readl(OSCR);
if(!event)
return 0xff000000;
@@ -226,9 +227,9 @@
* OSCR_CLK_FREQ, 1000);
while(1) {
- ndsr = NDSR;
+ ndsr = readl(NDSR);
if(ndsr & event) {
- NDSR |= event;
+ writel(readl(NDSR) | event, NDSR);
break;
}
if(get_delta(start) > timeout) {
@@ -248,11 +249,11 @@
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
- NDSR = 0xFFF;
+ writel(0xFFF, NDSR);
/* set NDCR[NDRUN] */
- if(!(NDCR & NDCR_ND_RUN))
- NDCR |= NDCR_ND_RUN;
+ if (!(readl(NDCR) & NDCR_ND_RUN))
+ writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
status = dfc_wait_event(NDSR_WRCMDREQ);
@@ -362,9 +363,9 @@
}
write_cmd:
- NDCB0 = ndcb0;
- NDCB0 = ndcb1;
- NDCB0 = ndcb2;
+ writel(ndcb0, NDCB0);
+ writel(ndcb1, NDCB0);
+ writel(ndcb2, NDCB0);
/* wait_event: */
dfc_wait_event(event);
@@ -377,36 +378,36 @@
DFC_DEBUG2("Setting up DFC GPIO's.\n");
/* no idea what is done here, see zylonite.c */
- GPIO4 = 0x1;
+ writel(0x1, GPIO4);
- DF_ALE_WE1 = 0x00000001;
- DF_ALE_WE2 = 0x00000001;
- DF_nCS0 = 0x00000001;
- DF_nCS1 = 0x00000001;
- DF_nWE = 0x00000001;
- DF_nRE = 0x00000001;
- DF_IO0 = 0x00000001;
- DF_IO8 = 0x00000001;
- DF_IO1 = 0x00000001;
- DF_IO9 = 0x00000001;
- DF_IO2 = 0x00000001;
- DF_IO10 = 0x00000001;
- DF_IO3 = 0x00000001;
- DF_IO11 = 0x00000001;
- DF_IO4 = 0x00000001;
- DF_IO12 = 0x00000001;
- DF_IO5 = 0x00000001;
- DF_IO13 = 0x00000001;
- DF_IO6 = 0x00000001;
- DF_IO14 = 0x00000001;
- DF_IO7 = 0x00000001;
- DF_IO15 = 0x00000001;
+ writel(0x00000001, DF_ALE_nWE1);
+ writel(0x00000001, DF_ALE_nWE2);
+ writel(0x00000001, DF_nCS0);
+ writel(0x00000001, DF_nCS1);
+ writel(0x00000001, DF_nWE);
+ writel(0x00000001, DF_nRE);
+ writel(0x00000001, DF_IO0);
+ writel(0x00000001, DF_IO8);
+ writel(0x00000001, DF_IO1);
+ writel(0x00000001, DF_IO9);
+ writel(0x00000001, DF_IO2);
+ writel(0x00000001, DF_IO10);
+ writel(0x00000001, DF_IO3);
+ writel(0x00000001, DF_IO11);
+ writel(0x00000001, DF_IO4);
+ writel(0x00000001, DF_IO12);
+ writel(0x00000001, DF_IO5);
+ writel(0x00000001, DF_IO13);
+ writel(0x00000001, DF_IO6);
+ writel(0x00000001, DF_IO14);
+ writel(0x00000001, DF_IO7);
+ writel(0x00000001, DF_IO15);
- DF_nWE = 0x1901;
- DF_nRE = 0x1901;
- DF_CLE_NOE = 0x1900;
- DF_ALE_WE1 = 0x1901;
- DF_INT_RnB = 0x1900;
+ writel(0x1901, DF_nWE);
+ writel(0x1901, DF_nRE);
+ writel(0x1900, DF_CLE_nOE);
+ writel(0x1901, DF_ALE_nWE1);
+ writel(0x1900, DF_INT_RnB);
}
/*
@@ -435,7 +436,7 @@
dfc_gpio_init();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
- CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+ writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
#undef CONFIG_SYS_TIMING_TIGHT
#ifndef CONFIG_SYS_TIMING_TIGHT
@@ -490,17 +491,19 @@
tRP_high = 0;
}
- NDTR0CS0 = (tCH << 19) |
+ writel((tCH << 19) |
(tCS << 16) |
(tWH << 11) |
(tWP << 8) |
(tRP_high << 6) |
(tRH << 3) |
- (tRP << 0);
+ (tRP << 0),
+ NDTR0CS0);
- NDTR1CS0 = (tR << 16) |
+ writel((tR << 16) |
(tWHR << 4) |
- (tAR << 0);
+ (tAR << 0),
+ NDTR1CS0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
@@ -517,7 +520,7 @@
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
- NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ writel(NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
(2 << 16) | /* read id count = 7 ???? mk@tbd */
@@ -533,7 +536,8 @@
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM); /* write command request ir masked */
+ NDCR_WRCMDREQM, /* write command request ir masked */
+ NDCR);
/* wait 10 us due to cmd buffer clear reset */