Makefile: convert makefiles to Kbuild style and delete grep switch

We have converted all makefiles needed to build $(LIBS).

Until this commit we used to grep switch so that U-Boot style
and Kbuild style makefiles coexist.
But we do not need any more.

Goint forward, use always Kbuild style Makefile when adding
a new Makefile

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
diff --git a/Makefile b/Makefile
index 7b05b53..a2fd7f6 100644
--- a/Makefile
+++ b/Makefile
@@ -559,32 +559,16 @@
 		$(GEN_UBOOT) $(obj)common/system_map.o
 endif
 
-# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
-#  U-Boot conventional sub makefiles always include some other makefiles.
-#  So, the build system searches a line beginning with "include" before entering into the sub makefile
-#  in order to distinguish which style it is.
-#  If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
-#  Otherwise, it is treated as a Kbuild-style makefile.
-select_makefile = \
-	+if grep -q "^include" $1/Makefile; then				\
-		$(MAKE) -C $1;						\
-	else								\
-		$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build;	\
-		mv $(dir $@)built-in.o $@;				\
-	fi
-
-# We do not need to build $(OBJS) explicitly.
-# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
-$(OBJS):	depend
-		if grep -q "^include" $(CPUDIR)/Makefile; then \
-			$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)); \
-		fi
+$(OBJS):
+	@:
 
 $(LIBS):	depend $(SUBDIR_TOOLS)
-		+$(call select_makefile, $(dir $(subst $(obj),,$@)))
+		$(MAKE) $(build) $(dir $(subst $(obj),,$@))
+		mv $(dir $@)built-in.o $@
 
 $(LIBBOARD):	depend $(LIBS)
-		+$(call select_makefile, $(dir $(subst $(obj),,$@)))
+		$(MAKE) $(build) $(dir $(subst $(obj),,$@))
+		mv $(dir $@)built-in.o $@
 
 $(SUBDIRS):	depend
 		$(MAKE) -C $@ all
@@ -612,13 +596,6 @@
 updater:
 		$(MAKE) -C tools/updater all
 
-select_makefile2 = \
-	if grep -q "^include" $1/Makefile; then					\
-		$(MAKE) -C $1 _depend;						\
-	else									\
-		$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build _depend;	\
-	fi
-
 # Explicitly make _depend in subdirs containing multiple targets to prevent
 # parallel sub-makes creating .depend files simultaneously.
 depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) \
@@ -627,9 +604,6 @@
 		$(obj)include/autoconf.mk \
 		$(obj)include/generated/generic-asm-offsets.h \
 		$(obj)include/generated/asm-offsets.h
-		+for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
-			$(call select_makefile2, $$dir); \
-		done
 
 TAG_SUBDIRS = $(SUBDIRS)
 TAG_SUBDIRS += $(dir $(__LIBS))