| commit | fa6539a3dcbf269121ca64084cff4c146fcdaf19 | [log] [tgz] |
|---|---|---|
| author | Amit Singh Tomar <amittomer25@gmail.com> | Sat May 09 19:55:11 2020 +0530 |
| committer | Tom Rini <trini@konsulko.com> | Tue Jul 07 16:09:22 2020 -0400 |
| tree | 7d69dd70983699384dda5b1ead1bf642c2924451 | |
| parent | b0778d9c2c221a13b7b977bd8eb397a16ff36fe0 [diff] |
net: phy: realtek: Introduce PHY_RTL8201F_S700_RMII_TIMINGS to adjust rx/tx timings RTL8201F PHY module found on Actions Semi Cubieboard7 seems to have specific Rx/Tx interface timings requirement for proper PHY operations. These timing values are not documented anywhere and picked from vendor code. This commits lets proper packets to be transmitted over the network. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>