| commit | 3e731aaba30c7011edf6391072eee845ed1b816f | [log] [tgz] |
|---|---|---|
| author | Dave Liu <daveliu@freescale.com> | Wed Dec 16 10:24:39 2009 -0600 |
| committer | Kumar Gala <galak@kernel.crashing.org> | Tue Jan 05 13:50:07 2010 -0600 |
| tree | ff32b3e1f2bbec7abfcd740f4dda254bd92cf0ab | |
| parent | 1aa3d08a0244506b94031522e54fe06ee7a5ae0e [diff] |
fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>