Tegra: clocks: Add 38.4MHz OSC support for T210 use
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).
Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected since they're not viable T210 OSC freqs.
Since there are now 2 new OSC defines, all tables (pll_x_table,
PLLU) had to increase by two entries, but since 38.4/48MHz are
not viable osc freqs on T20/30/114, etc, they're just set to 0.
Signed-off-by: Tom Warren <twarren@nvidia.com>
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 4e7d793..7ac2a06 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -649,8 +649,8 @@
*/
if (reg == 5) {
debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
- /* Map it to 19.2MHz for now. 38.4MHz OSC support TBD */
- return 1;
+ /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
+ return 4;
}
/*
@@ -930,6 +930,10 @@
clock_set_rate(CLOCK_ID_CGENERAL, 125, 4, 0, 0);
clock_set_rate(CLOCK_ID_DISPLAY, 96, 2, 0, 12);
break;
+ case CLOCK_OSC_FREQ_38_4:
+ clock_set_rate(CLOCK_ID_CGENERAL, 125, 8, 0, 0);
+ clock_set_rate(CLOCK_ID_DISPLAY, 96, 4, 0, 0);
+ break;
default:
/*
* These are not supported. It is too early to print a