powerpc/85xx: Add basic support for P1023RDS board
The P1023RDS board is the reference board for the P1023 SoC.
Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe,
UART, I2C, etc.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/board/freescale/p1023rds/Makefile b/board/freescale/p1023rds/Makefile
new file mode 100644
index 0000000..bf87580
--- /dev/null
+++ b/board/freescale/p1023rds/Makefile
@@ -0,0 +1,38 @@
+#
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1023rds/bcsr.h b/board/freescale/p1023rds/bcsr.h
new file mode 100644
index 0000000..0995aa4
--- /dev/null
+++ b/board/freescale/p1023rds/bcsr.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Authors: Chunhe Lan <b25806@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/*
+ * BCSR Bit definitions
+ * BCSR 15 *
+ 0 device insertion oriention
+ 1 stack processor present
+ 2 power supply shut down/normal operation
+ 3 I2C bus0 drive enable
+ 4 reserved
+ 5:7 I2C bus0 select
+ 5 - I2C_BUS_0_SS0
+ 6 - I2C_BUS_0_SS1
+ 7 - I2C_BUS_0_SS2
+*/
+
+/* BCSR register base address is 0xFX000020 */
+#define BCSR_BASE_REG_OFFSET 0x20
+#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET)
+
+#define BCSR15_DEV_INS_ORI 0x80
+#define BCSR15_STACK_PRO_PRE 0x40
+#define BCSR15_POWER_SUPPLY 0x20
+#define BCSR15_I2C_BUS0_EN 0x10
+#define BCSR15_I2C_BUS0_SEG0 0x00
+#define BCSR15_I2C_BUS0_SEG1 0x04
+#define BCSR15_I2C_BUS0_SEG2 0x02
+#define BCSR15_I2C_BUS0_SEG3 0x06
+#define BCSR15_I2C_BUS0_SEG4 0x01
+#define BCSR15_I2C_BUS0_SEG5 0x05
+#define BCSR15_I2C_BUS0_SEG6 0x03
+#define BCSR15_I2C_BUS0_SEG7 0x07
+#define BCSR15_I2C_BUS0_SEG_CLR 0x07
+#define BCSR19_SGMII_SEL_L 0x01
+
+/*BCSR Utils functions*/
+void fixup_i2c_bus0_sel_seg0(void);
+#endif /* __BCSR_H_ */
diff --git a/board/freescale/p1023rds/law.c b/board/freescale/p1023rds/law.c
new file mode 100644
index 0000000..f140f64
--- /dev/null
+++ b/board/freescale/p1023rds/law.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
+ LAW_TRGT_IF_DPAA_SWP_SRAM),
+ /* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */
+ SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
new file mode 100644
index 0000000..8cfd199
--- /dev/null
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Authors: Roy Zang <tie-fei.zang@freescale.com>
+ * Chunhe Lan <b25806@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_portals.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <malloc.h>
+
+#include "bcsr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ /* Set ABSWP to implement conversion of addresses in the LBC */
+ setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
+
+ printf("Board: P1023 RDS\n");
+
+ clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR);
+ setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0);
+
+ return 0;
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+#ifndef CONFIG_SYS_RAMBOOT
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+
+ set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
+
+ out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+ out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
+ out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
+ out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+ out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
+ out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
+ out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
+ out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+ out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
+ out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+ out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+ out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
+ out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
+ out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
+ out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+#endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_BCSR_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + BCSR region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + bcsr */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ setup_portals();
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ return gd->bus_clk;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ return gd->mem_clk;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+}
+#endif
diff --git a/board/freescale/p1023rds/tlb.c b/board/freescale/p1023rds/tlb.c
new file mode 100644
index 0000000..2b3b679
--- /dev/null
+++ b/board/freescale/p1023rds/tlb.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_4M, 1),
+
+#ifndef CONFIG_NAND_SPL
+ /* *W*G* - BCSR and NOR flash on local bus*/
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 9, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+ CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_1G, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_1G, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);