ARM: uniphier: add a field to specify DDR3+
Add a field to distinguish DDR3+ from (standard) DDR3. It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).
Default DDR3 spec for each SoC:
PH1-LD4, PH1-sLD8: DDR3+
Others: DDR3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
index fa0619f..3cbb7ba 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c
@@ -48,15 +48,10 @@
}
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
- int size, int freq)
+ int size, int freq, bool ddr3plus)
{
-#ifdef CONFIG_DDR_STANDARD
- writel(0x55990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958944, dramcont + UMC_CMDCTLB);
-#else
- writel(0x45990b11, dramcont + UMC_CMDCTLA);
- writel(0x16958924, dramcont + UMC_CMDCTLB);
-#endif
+ writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA);
+ writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB);
if (size == 1)
writel(0x00240512, dramcont + UMC_SPCCTLA);
@@ -85,7 +80,7 @@
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
@@ -102,20 +97,20 @@
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
- ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0);
+ ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
ddrphy_prepare_training(phy0_0, 0);
ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
- ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1);
+ ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
ddrphy_prepare_training(phy1_0, 1);
ddrphy_training(phy1_0);
- umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
- umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+ umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq, ddr3plus);
+ umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq, ddr3plus);
umc_start_ssif(ssif_base);
@@ -130,7 +125,8 @@
bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
return umc_init_sub(bd->dram_freq,
bd->dram_ch[0].size / SZ_128M,
- bd->dram_ch[1].size / SZ_128M);
+ bd->dram_ch[1].size / SZ_128M,
+ bd->dram_ddr3plus);
} else {
pr_err("Unsupported DDR configuration\n");
return -EINVAL;