Merge git://git.denx.de/u-boot-socfpga
Conflicts:
include/configs/axs101.h
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 224928f..a202709 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -34,6 +34,10 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
};
&gmac1 {
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index e50fbd8..2f070f2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -65,12 +65,13 @@
*/
#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6)
#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8)
#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index b110f5b..9b43b92 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -54,14 +54,23 @@
void v7_outer_cache_enable(void)
{
- /* disable the L2 cache */
- writel(0, &pl310->pl310_ctrl);
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |
L310_AUX_CTRL_INST_PREFETCH_MASK |
L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+ /* Enable the L2 cache */
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ /* Disable the L2 cache */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
/*
@@ -350,6 +359,10 @@
socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
#endif
+#ifdef CONFIG_NAND_DENALI
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+#endif
+
return 0;
}
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 775a827..98c16a0 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -40,6 +40,7 @@
return BOOT_DEVICE_RAM;
case 0x2: /* NAND Flash (1.8V) */
case 0x3: /* NAND Flash (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
return BOOT_DEVICE_NAND;
case 0x4: /* SD/MMC External Transceiver (1.8V) */
case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 33cf1fd..f1e6d2b 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -9,19 +9,19 @@
const u8 sys_mgr_init_table[] = {
3, /* EMACIO0 */
- 3, /* EMACIO1 */
- 3, /* EMACIO2 */
- 3, /* EMACIO3 */
- 3, /* EMACIO4 */
- 3, /* EMACIO5 */
- 3, /* EMACIO6 */
- 3, /* EMACIO7 */
- 3, /* EMACIO8 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
3, /* EMACIO9 */
- 3, /* EMACIO10 */
- 3, /* EMACIO11 */
- 3, /* EMACIO12 */
- 3, /* EMACIO13 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
0, /* EMACIO14 */
0, /* EMACIO15 */
0, /* EMACIO16 */
@@ -55,8 +55,8 @@
0, /* GENERALIO12 */
2, /* GENERALIO13 */
2, /* GENERALIO14 */
- 0, /* GENERALIO15 */
- 0, /* GENERALIO16 */
+ 3, /* GENERALIO15 */
+ 3, /* GENERALIO16 */
2, /* GENERALIO17 */
2, /* GENERALIO18 */
0, /* GENERALIO19 */
@@ -72,27 +72,27 @@
0, /* GENERALIO29 */
0, /* GENERALIO30 */
0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 1, /* MIXED1IO1 */
- 1, /* MIXED1IO2 */
- 1, /* MIXED1IO3 */
- 1, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 1, /* MIXED1IO8 */
- 1, /* MIXED1IO9 */
- 1, /* MIXED1IO10 */
- 1, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
0, /* MIXED1IO14 */
- 1, /* MIXED1IO15 */
- 1, /* MIXED1IO16 */
- 1, /* MIXED1IO17 */
- 1, /* MIXED1IO18 */
- 0, /* MIXED1IO19 */
- 0, /* MIXED1IO20 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
0, /* MIXED2IO0 */
0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 3d621ed..4abd2e0 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
@@ -31,7 +31,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index fc0918f..858a9ca 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -48,9 +48,6 @@
#if defined(CONFIG_ETH_DESIGNWARE)
u32 interface = PHY_INTERFACE_MODE_MII;
-#if defined(CONFIG_DW_AUTONEG)
- interface = PHY_INTERFACE_MODE_GMII;
-#endif
if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
ret++;
#endif
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 10eb91d..68d12df 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -11,6 +11,7 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -23,3 +24,4 @@
CONFIG_DM_MMC=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 864358c..accee92 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -11,6 +11,7 @@
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
@@ -23,3 +24,4 @@
CONFIG_DM_MMC=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 2c75bda..3d98a63 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -17,3 +17,4 @@
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_MMC=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ae5e78d..de54ca8 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -88,6 +88,7 @@
config ETH_DESIGNWARE
bool "Synopsys Designware Ethernet MAC"
+ select PHYLIB
help
This MAC is present in SoCs from various vendors. It supports
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index a6c39c3..04114a1 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -22,10 +22,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_PHYLIB)
-# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
-#endif
-
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
struct eth_mac_regs *mac_p = bus->priv;
@@ -107,8 +103,8 @@
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
- DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
- DESC_TXSTS_TXCHECKINSCTRL | \
+ DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
+ DESC_TXSTS_TXCHECKINSCTRL |
DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
@@ -155,7 +151,7 @@
desc_p->dmamac_next = &desc_table_p[idx + 1];
desc_p->dmamac_cntl =
- (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
+ (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
DESC_RXCTRL_RXCHAIN;
desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
@@ -321,14 +317,14 @@
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
- desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
+ desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
DESC_TXCTRL_SIZE1MASK;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
- desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
- DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
+ desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
+ DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
DESC_TXCTRL_TXFIRST;
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
@@ -368,7 +364,7 @@
/* Check if the owner is the CPU */
if (!(status & DESC_RXSTS_OWNBYDMA)) {
- length = (status & DESC_RXSTS_FRMLENMSK) >> \
+ length = (status & DESC_RXSTS_FRMLENMSK) >>
DESC_RXSTS_FRMLENSHFT;
/* Invalidate received data */
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index c92cca2..98fff63 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -95,16 +95,10 @@
/*
* Ethernet PHY configuration
*/
-#define CONFIG_PHYLIB
#define CONFIG_MII
#define CONFIG_PHY_GIGE
/*
- * Ethernet configuration
- */
-#define CONFIG_DW_AUTONEG
-
-/*
* USB 1.1 configuration
*/
#define CONFIG_USB_OHCI_NEW
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 0e353b9..b5d4847 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -75,7 +75,6 @@
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_CMD_MII
#define CONFIG_MII
-#define CONFIG_PHYLIB
/* i2c Settings */
#define CONFIG_SYS_I2C
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index eb16a5e..14a42b1 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -45,7 +45,6 @@
/* 10/100M Ethernet support */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_PHYLIB
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index 3d5665d..a0161bc 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -52,8 +52,6 @@
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -72,11 +70,13 @@
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 3a4df63..a09e906 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -109,7 +109,6 @@
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
-#define CONFIG_PHYLIB
#define CONFIG_PHY_GIGE
#endif
@@ -162,6 +161,19 @@
#endif
/*
+ * NAND Support
+ */
+#ifdef CONFIG_NAND_DENALI
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_DENALI_ECC_SIZE 512
+#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
+#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
+#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
+#endif
+
+/*
* I2C support
*/
#define CONFIG_SYS_I2C
@@ -197,7 +209,7 @@
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define MTDIDS_DEFAULT "nor0=ff705000.spi"
+#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
@@ -249,7 +261,9 @@
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_FUNCTION_DFU
+#ifdef CONFIG_DM_MMC
#define CONFIG_DFU_MMC
+#endif
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
@@ -271,6 +285,43 @@
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
#define CONFIG_ENV_SIZE 4096
+/* Environment for SDMMC boot */
+#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+#endif
+
+/*
+ * mtd partitioning for serial NOR flash
+ *
+ * device nor0 <ff705000.spi.0>, # parts = 6
+ * #: name size offset mask_flags
+ * 0: u-boot 0x00100000 0x00000000 0
+ * 1: env1 0x00040000 0x00100000 0
+ * 2: env2 0x00040000 0x00140000 0
+ * 3: UBI 0x03e80000 0x00180000 0
+ * 4: boot 0x00e80000 0x00180000 0
+ * 5: rootfs 0x01000000 0x01000000 0
+ *
+ */
+#if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
+#define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\
+ "1m(u-boot)," \
+ "256k(env1)," \
+ "256k(env2)," \
+ "14848k(boot)," \
+ "16m(rootfs)," \
+ "-@1536k(UBI)\0"
+#endif
+
+/* UBI and UBIFS support */
+#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#endif
+
/*
* SPL
*
@@ -294,8 +345,15 @@
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#ifdef CONFIG_DM_MMC
#define CONFIG_SPL_MMC_SUPPORT
+#endif
+#ifdef CONFIG_DM_SPI
#define CONFIG_SPL_SPI_SUPPORT
+#endif
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
@@ -318,6 +376,13 @@
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#endif
+/* SPL NAND boot support */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#endif
+
/*
* Stack setup
*/
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index d2efdda..c4c4ecb 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -52,8 +52,6 @@
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -72,11 +70,13 @@
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index 959e3af..cbc7396 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -48,8 +48,6 @@
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index cd63faf..e7b5675 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -45,8 +45,6 @@
/* Environment is in MMC */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 6cbe367..95e7ba6 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -48,8 +48,6 @@
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -68,6 +66,13 @@
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index 1d88f4f..c32a40a 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -48,8 +48,6 @@
#endif
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index 5bd2956..fdf67ca 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -70,11 +70,13 @@
"mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
- "qspiroot=/dev/mtdblock0\0" \
- "qspirootfstype=jffs2\0" \
+ "qspiload=sf probe && mtdparts default && run ubiload\0" \
"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
- " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
- "bootm ${loadaddr} - ${fdt_addr}\0"
+ " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "ubiload=ubi part UBI && ubifsmount ubi0 && " \
+ "ubifsload ${loadaddr} /boot/${bootimage} && " \
+ "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
/* Environment */
#define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 1d69477..d2630f4 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -17,7 +17,6 @@
/* Ethernet driver configuration */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index 14c6a9e..f421321 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -53,7 +53,6 @@
/* GMAC related configs */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_PHY_MICREL
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 8042073..790e704 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -309,11 +309,9 @@
#endif
#ifdef CONFIG_SUNXI_GMAC
-#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
-#define CONFIG_PHYLIB
#endif
#ifdef CONFIG_USB_EHCI_HCD
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 8660ed4..e06484f 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -42,7 +42,6 @@
/*
* Ethernet PHY configuration
*/
-#define CONFIG_PHYLIB
#define CONFIG_PHY_GIGE
/*
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 58f1aca..0263c50 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -77,7 +77,6 @@
/* Ethernet config options */
#define CONFIG_MII
-#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */