net: ftgmac100: Modify desc. size to cache line
The TX/RX descriptor size is 16 byte.
When the cache line size is larger than 16 bytes, descriptors
flushed to RAM will flush more than one descriptor.
It is possible that it may mistakenly flush to other descriptor
that has been updated by MAC in RAM.
To avoid this issue, align the descriptors to cache line size.
Only one desc will be flushed or invalidated at a time.
Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 3920161..9d64125 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -321,7 +321,7 @@
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct phy_device *phydev = priv->phydev;
- unsigned int maccr;
+ unsigned int maccr, dblac, desc_size;
ulong start, end;
int ret;
int i;
@@ -366,6 +366,17 @@
/* receive ring */
writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
+ /* Configure TX/RX decsriptor size
+ * This size is calculated based on cache line.
+ */
+ desc_size = ARCH_DMA_MINALIGN / FTGMAC100_DESC_UNIT;
+ /* The descriptor size is at least 2 descriptor units. */
+ if (desc_size < 2)
+ desc_size = 2;
+ dblac = readl(&ftgmac100->dblac) & ~GENMASK(19, 12);
+ dblac |= FTGMAC100_DBLAC_RXDES_SIZE(desc_size) | FTGMAC100_DBLAC_TXDES_SIZE(desc_size);
+ writel(dblac, &ftgmac100->dblac);
+
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);