| commit | 426230a65f2dd62c3b6c1509e9775d5500db20d3 | [log] [tgz] |
|---|---|---|
| author | York Sun <york.sun@nxp.com> | Mon Jan 29 09:44:33 2018 -0800 |
| committer | York Sun <york.sun@nxp.com> | Tue Jan 30 09:14:06 2018 -0800 |
| tree | 1f500bcdf25fc0ed2a5840bcdecd558173de9da1 | |
| parent | a9b1c2164a45e0c1af59b8e7a1c92f2f53babe92 [diff] |
drivers/ddr/fsl: Fix DDR4 RDIMM support For DDR4, command/address delay in mode registers and parity latency in timing config register are only needed for UDIMMs, but not RDIMMs. Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix calculation of timing config registers. Use hexadecimal format for printing RCW (register control word) registers. Signed-off-by: York Sun <york.sun@nxp.com>