mpc83xx: Get rid of CONFIG_SYS_LBC_*
Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value
of either 0x00040000 or 0x00000000.
CONFIG_SYS_LBC_MRTPR always has the value 0x20000000.
CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board.
CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000).
To simplify the configuration files, hardcode the setting of these
values for mpc83xx.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index f14276f..913b584 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -183,28 +183,36 @@
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
+ const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+ LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+ LSDMR_WRC3 | LSDMR_CL3;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->lbcr = 0x00000000;
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
+ /* LB sdram refresh timer, about 6us */
+ lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+ /* 0x68636733; precharge all the banks */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ /* 0x48636733; auto refresh */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
@@ -232,12 +240,13 @@
udelay(100);
/* 0x58636733; mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);