riscv: ax25: Hide the ax25-specific Kconfig option
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6c7022f..e9dbca2 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,7 +1,14 @@
config RISCV_NDS
- bool "AndeStar V5 ISA support"
- default n
+ bool
help
- Say Y here if you plan to run U-Boot on AndeStar v5
- platforms and use some specific features which are
- provided by Andes Technology AndeStar V5 Families.
+ Run U-Boot on AndeStar V5 platforms and use some specific features
+ which are provided by Andes Technology AndeStar V5 families.
+
+if RISCV_NDS
+
+config RISCV_NDS_CACHE
+ bool "AndeStar V5 families specific cache support"
+ help
+ Provide Andes Technology AndeStar V5 families specific cache support.
+
+endif