riscv: mbv: Enable SPL and binman
Enable SPL and binman to generate u-boot.img (machine mode) and u-boot.itb
(supervisor mode). DTB is placed at fixed address to ensure that it is 8
byte aligned which is not ensured when dtb is attached behind SPL binary
that's why SPL and U-Boot are taking DTB from the same address.
Also align addresses for both defconfigs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/85506bce5580d448f095f267d029e3932c5e9990.1707911544.git.michal.simek@amd.com
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 9641ed3..e5ab32f 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -358,6 +358,14 @@
void *fdt_blob;
*err = 0;
+
+ if (IS_ENABLED(CONFIG_TARGET_XILINX_MBV)) {
+ fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
+
+ if (fdt_magic(fdt_blob) == FDT_MAGIC)
+ return fdt_blob;
+ }
+
if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
!IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
!IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {