commit 47bf9c71ae838305a3ea3161af8d14e6f3fc2c82
author TsiChung Liew <Tsi-Chung.Liew@freescale.com> Wed Jul 09 16:20:23 2008 -0500
committer John Rigby <jrigby@freescale.com> Fri Jul 11 10:45:59 2008 -0600
tree 0768c1f95aa63e5a759d486bd9ff7ee24fd88da8
parent bc3ccb139f0836f0a834cfd370a120a00ad7e63a

ColdFire: Fix FB CS not setup properly for Mcf5282

Remove all CFG_CSn_RO in cpu/mcf52x2/cpu_init.c. If
CFG_CSn_RO is defined as 0, the chipselect will not
be assigned.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

cpu/mcf52x2/cpu_init.c

diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 207a37e..344bcee 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -419,8 +419,7 @@
 	   else is doing it! */
 
 #if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
-    defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
-	defined(CFG_CS0_WS)
+    defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
 
 	MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
 
@@ -447,8 +446,7 @@
 #endif
 
 #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
-    defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
-	defined(CFG_CS1_WS)
+    defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
 
 	MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
 
@@ -476,8 +474,7 @@
 #endif
 
 #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
-    defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
-	defined(CFG_CS2_WS)
+    defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
 
 	MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
 
@@ -505,8 +502,7 @@
 #endif
 
 #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
-    defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
-	defined(CFG_CS3_WS)
+    defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
 
 	MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;