commit 480ed1dea103a1c8f4591afc77d2de3c7868d983
author David Brownell <david-b@pacbell.net> Fri Jan 18 12:55:00 2008 -0800
committer Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Sun Mar 30 15:38:05 2008 +0200
tree 3742d043b46f92c9767505d92e6f1ace8bd66954
parent a3543d6dc52b0ba9c64016687cf32d600b31a476

use correct at91rm9200 register name

This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2.  This
makes code use the register name from chip datasheets.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

include/configs/at91rm9200dk.h

diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 5b7212a..951ce16 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -51,7 +51,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */

include/configs/cmc_pu2.h

diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index d22d350..bce5fcd 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -50,7 +50,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */

include/configs/csb637.h

diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index f93c3bc..e9c6d8e 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -51,7 +51,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x2031BE01 /* 184.320000 MHz for PCK */

include/configs/mp2usb.h

diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 294221f..2eb4af1 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -55,7 +55,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */