Further NAND stuff implemented. Basic read commands seem to work.
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 05ed969..6236405 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -2083,26 +2083,28 @@
#define NDCR_DWIDTH_M (0x1<<26)
#define NDCR_PAGE_SZ (0x3<<24)
#define NDCR_NCSX (0x1<<23)
-#define NDCR_ND_MODE (0x3<<21)
-#define NDCR_NAND_MODE 0x0
+#define NDCR_ND_STOP (0x1<<22)
+/* reserved:
+ * #define NDCR_ND_MODE (0x3<<21)
+ * #define NDCR_NAND_MODE 0x0 */
#define NDCR_CLR_PG_CNT (0x1<<20)
#define NDCR_CLR_ECC (0x1<<19)
#define NDCR_RD_ID_CNT (0x7<<16)
#define NDCR_RA_START (0x1<<15)
#define NDCR_PG_PER_BLK (0x1<<14)
#define NDCR_ND_ARB_EN (0x1<<12)
-#define NDCE_RDYM (0x1<<11)
-#define NDCE_CS0_PAGEDM (0x1<<10)
-#define NDCE_CS1_PAGEDM (0x1<<9)
-#define NDCE_CS0_CMDDM (0x1<<8)
-#define NDCE_CS1_CMDDM (0x1<<7)
-#define NDCE_CS0_BBDM (0x1<<6)
-#define NDCE_CS1_BBDM (0x1<<5)
-#define NDCE_DBERRM (0x1<<4)
-#define NDCE_SBERRM (0x1<<3)
-#define NDCE_WRDREQM (0x1<<2)
-#define NDCE_RDDREQM (0x1<<1)
-#define NDCE_WRCMDREQM (0x1)
+#define NDCR_RDYM (0x1<<11)
+#define NDCR_CS0_PAGEDM (0x1<<10)
+#define NDCR_CS1_PAGEDM (0x1<<9)
+#define NDCR_CS0_CMDDM (0x1<<8)
+#define NDCR_CS1_CMDDM (0x1<<7)
+#define NDCR_CS0_BBDM (0x1<<6)
+#define NDCR_CS1_BBDM (0x1<<5)
+#define NDCR_DBERRM (0x1<<4)
+#define NDCR_SBERRM (0x1<<3)
+#define NDCR_WRDREQM (0x1<<2)
+#define NDCR_RDDREQM (0x1<<1)
+#define NDCR_WRCMDREQM (0x1)
#define NDSR_RDY (0x1<<11)
#define NDSR_CS0_PAGED (0x1<<10)
@@ -2111,7 +2113,7 @@
#define NDSR_CS1_CMDD (0x1<<7)
#define NDSR_CS0_BBD (0x1<<6)
#define NDSR_CS1_BBD (0x1<<5)
-#define NDSR_BDERR (0x1<<4)
+#define NDSR_DBERR (0x1<<4)
#define NDSR_SBERR (0x1<<3)
#define NDSR_WRDREQ (0x1<<2)
#define NDSR_RDDREQ (0x1<<1)