commit 48b42616e928ce6eacfe20276a1614e2b27ac4b5
author wdenk <wdenk> Thu Jun 19 23:01:32 2003 +0000
committer wdenk <wdenk> Thu Jun 19 23:01:32 2003 +0000
tree 0c194fbd1059185f158c0b37dc3c846b50c2ee2f
parent 15ef8a5d17181ea376fac94579dce0af1cfcdeb7

* Patches by David Müller, 12 Jun 2003:
  - rewrite of the S3C24X0 register definitions stuff
  - "driver" for the built-in S3C24X0 RTC

* Patches by Yuli Barcohen, 12 Jun 2003:
  - Add MII support and Ethernet PHY initialization for MPC8260ADS board
  - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
    configuration word supplied by FPGA on some MPC8260ADS boards

* Patch by Pantelis Antoniou, 10 Jun 2003:
  Unify status LED interface

cpu/arm920t/speed.c

diff --git a/cpu/arm920t/speed.c b/cpu/arm920t/speed.c
index 4942727..1f43543 100644
--- a/cpu/arm920t/speed.c
+++ b/cpu/arm920t/speed.c
@@ -51,12 +51,13 @@
 
 static ulong get_PLLCLK(int pllreg)
 {
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
     ulong r, m, p, s;
 
     if (pllreg == MPLL)
-	r = rMPLLCON;
+	r = clk_power->MPLLCON;
     else if (pllreg == UPLL)
-	r = rUPLLCON;
+	r = clk_power->UPLLCON;
     else
 	hang();
 
@@ -76,17 +77,17 @@
 /* return HCLK frequency */
 ulong get_HCLK(void)
 {
-    ulong clkdiv = rCLKDIVN;
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
-    return((clkdiv & 0x2) ? get_FCLK()/2 : get_FCLK());
+    return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
 }
 
 /* return PCLK frequency */
 ulong get_PCLK(void)
 {
-    ulong clkdiv = rCLKDIVN;
+    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 
-    return((clkdiv & 0x1) ? get_HCLK()/2 : get_HCLK());
+    return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
 }
 
 /* return UCLK frequency */