powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun <yorksun@freescale.com>
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index 36c8545..10c5a42 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -101,7 +101,7 @@
cpu = gd->cpu;
/* P1014 and it's derivatives support max 16it DDR width */
- if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E)
+ if (cpu->soc_ver == SVR_P1014)
ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
else
ddr_size = CONFIG_SYS_DRAM_SIZE;
@@ -146,7 +146,7 @@
cpu = gd->cpu;
/* P1014 and it's derivatives support max 16bit DDR width */
- if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {
+ if (cpu->soc_ver == SVR_P1014) {
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000;
@@ -238,7 +238,7 @@
cpu = gd->cpu;
/* P1014 and it's derivatives support max 16it DDR width */
- if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E)
+ if (cpu->soc_ver == SVR_P1014)
popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {