ppc4xx: Change Canyonlands to support booting from 2k page NAND devices
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c
index 37fa1c9..1d125b6 100644
--- a/board/amcc/canyonlands/bootstrap.c
+++ b/board/amcc/canyonlands/bootstrap.c
@@ -63,9 +63,22 @@
/*
* Bytes 5,6,8,9,11 change for NAND boot
*/
+#if 0
+/*
+ * Values for 512 page size NAND chips, not used anymore, just
+ * keep them here for reference
+ */
static u8 nand_boot[] = {
0x90, 0x01, 0xa0, 0x68, 0x58
};
+#else
+/*
+ * Values for 2k page size NAND chips
+ */
+static u8 nand_boot[] = {
+ 0x90, 0x01, 0xa0, 0xe8, 0x58
+};
+#endif
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index bd4cab5..258fb5d 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -51,6 +51,7 @@
#else
tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
#endif
/*
diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds
index f0837d4..332e3aa 100644
--- a/board/amcc/canyonlands/u-boot-nand.lds
+++ b/board/amcc/canyonlands/u-boot-nand.lds
@@ -56,10 +56,10 @@
cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
- . = ALIGN(0x4000);
+ . = ALIGN(0x20000);
common/environment.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
- . = ALIGN(0x10000);
+ . = ALIGN(0x80000);
*(.text)
*(.fixup)