ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig
This commit converts the following items to Kconfig:
CONFIG_ATMEL_NAND_HWECC
CONFIG_ATMEL_NAND_HW_PMECC
CONFIG_PMECC_CAP
CONFIG_PMECC_SECTOR_SIZE
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
[PMECC References]
https://www.at91.com/linux4sam/bin/view/Linux4SAM/PmeccConfigure
https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap
[Mailing List Thread]
https://lists.denx.de/pipermail/u-boot/2018-December/350666.html
Fixes: 5541543f ("configs: at91: Remove CONFIG_SYS_EXTRA_OPTIONS assignment")
[trini: Make the migration be size neutral and possibly not fix the
above in all cases]
Reported-by: Daniel Evans <photonthunder@gmail.com>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index ffc6cc9..6d46660 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -22,6 +22,44 @@
Enable this driver for NAND flash platforms using an Atmel NAND
controller.
+if NAND_ATMEL
+
+config ATMEL_NAND_HWECC
+ bool "Atmel Hardware ECC"
+ default n
+
+config ATMEL_NAND_HW_PMECC
+ bool "Atmel Programmable Multibit ECC (PMECC)"
+ select ATMEL_NAND_HWECC
+ default n
+ help
+ The Programmable Multibit ECC (PMECC) controller is a programmable
+ binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
+
+config PMECC_CAP
+ int "PMECC Correctable ECC Bits"
+ depends on ATMEL_NAND_HW_PMECC
+ default 2
+ help
+ Correctable ECC bits, can be 2, 4, 8, 12, and 24.
+
+config PMECC_SECTOR_SIZE
+ int "PMECC Sector Size"
+ depends on ATMEL_NAND_HW_PMECC
+ default 512
+ help
+ Sector size, in bytes, can be 512 or 1024.
+
+config SPL_GENERATE_ATMEL_PMECC_HEADER
+ bool "Atmel PMECC Header Generation"
+ select ATMEL_NAND_HWECC
+ select ATMEL_NAND_HW_PMECC
+ default n
+ help
+ Generate Programmable Multibit ECC (PMECC) header for SPL image.
+
+endif
+
config NAND_DAVINCI
bool "Support TI Davinci NAND controller"
help