| commit | 49fb28a4b29ee40e38eb92a1dcb69058ce4637af | [log] [tgz] |
|---|---|---|
| author | Bin Meng <bmeng.cn@gmail.com> | Sat Mar 28 07:25:29 2020 -0700 |
| committer | Tom Rini <trini@konsulko.com> | Fri Apr 10 15:54:16 2020 -0400 |
| tree | 1a2b5826d92e13bfae2232ef0c5c13000a966648 | |
| parent | b2c2608161c997a1ffeb2091ff77c845f602524d [diff] |
azure/gitlab/travis: Add RISC-V SPL testing This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64, we test SPL running in M-mode and U-Boot proper running in S-mode, with a 4-core SMP configuration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>