pinctrl: Add i.MX7ULP pinctrl driver

Add i.MX7ULP pinctrl driver.
Select CONFIG_PINCTRL_IMX7ULP to use this driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by : Stefano Babic <sbabic@denx.de>
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c
index e130faf..f0321c4 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -24,6 +24,7 @@
 	u32 *pin_data;
 	int npins, size, pin_size;
 	int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
+	u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
 	int i, j = 0;
 
 	dev_dbg(dev, "%s: %s\n", __func__, config->name);
@@ -97,8 +98,8 @@
 
 		/* Set Mux */
 		if (info->flags & SHARE_MUX_CONF_REG) {
-			clrsetbits_le32(info->base + mux_reg, 0x7 << 20,
-					mux_mode << 20);
+			clrsetbits_le32(info->base + mux_reg, info->mux_mask,
+					mux_mode << mux_shift);
 		} else {
 			writel(mux_mode, info->base + mux_reg);
 		}
@@ -154,8 +155,8 @@
 		/* Set config */
 		if (!(config_val & IMX_NO_PAD_CTL)) {
 			if (info->flags & SHARE_MUX_CONF_REG) {
-				clrsetbits_le32(info->base + conf_reg, 0xffff,
-						config_val);
+				clrsetbits_le32(info->base + conf_reg,
+						info->mux_mask, config_val);
 			} else {
 				writel(config_val, info->base + conf_reg);
 			}
@@ -200,6 +201,7 @@
 		return -ENOMEM;
 	priv->info = info;
 
+	info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
 	/*
 	 * Refer to linux documentation for details:
 	 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt