global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index 0613b77..d883b18 100644
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -77,17 +77,17 @@
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
/* NAND Flash Definitions */
-#define CONFIG_SYS_NAND_BASE 0x68000000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE 0x68000000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+#define CFG_SYS_NAND_CSPR_EXT (0x0)
+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_TE | \
CSPR_MSEL_NAND | \
CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
+#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
| CSOR_NAND_ECC_DEC_EN \
| CSOR_NAND_ECC_MODE_4 \
| CSOR_NAND_RAL_3 \
@@ -97,29 +97,29 @@
| CSOR_NAND_TRHZ_40 \
| CSOR_NAND_BCTLD)
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
FTIM0_NAND_TWP(0x8) | \
FTIM0_NAND_TWCHT(0x3) | \
FTIM0_NAND_TWH(0x5))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
FTIM1_NAND_TWBE(0x1e) | \
FTIM1_NAND_TRR(0x6) | \
FTIM1_NAND_TRP(0x8))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
FTIM2_NAND_TREH(0x5) | \
FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */
#define CONFIG_SYS_QRIO_BASE 0x70000000