riscv: dts: sync mpfs-icicle devicetree with linux
The "notable" disappearances are:
- the pac193x stanza - there's nothing in mainline linux w.r.t. bindings
for this & what is going to appear in mainline linux is going to be
incompatible with what is currently in U-Boot.
- operating points - these operating points should not be set at the
soc.dtsi level as they may not be possible depending on the design
programmed to the FPGA
- clock output names - there are defines for the clock indices, these
should not be needed
- the dt maintainers in linux NAKed using defines for IRQ numbers
- the qspi nand, which is not part of the icicle's default configuration
is removed.
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts
index 3c56400..8aa5fb1 100644
--- a/arch/riscv/dts/mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/mpfs-icicle-kit.dts
@@ -7,29 +7,63 @@
/dts-v1/;
#include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-reference-rtlv2210",
- "microchip,mpfs-icicle-kit", "microchip,mpfs";
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+ "microchip,mpfs";
aliases {
- serial1 = &uart1;
ethernet0 = &mac1;
- spi0 = &qspi;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
};
chosen {
- stdout-path = "serial1";
+ stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
+ leds {
+ compatible = "gpio-leds";
+
+ led-1 {
+ gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ label = "led1";
+ };
+
+ led-2 {
+ gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ label = "led2";
+ };
+
+ led-3 {
+ gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ label = "led3";
+ };
+
+ led-4 {
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ label = "led4";
+ };
+ };
+
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
@@ -54,83 +88,121 @@
};
};
-&refclk {
- clock-frequency = <125000000>;
+&core_pwm0 {
+ status = "okay";
};
-&uart1 {
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+ status = "enabled";
+};
+
+&mac1 {
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+ status = "okay";
+
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ };
+
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+&mbox {
status = "okay";
};
&mmc {
- status = "okay";
-
bus-width = <4>;
disable-wp;
- cap-mmc-highspeed;
cap-sd-highspeed;
- card-detect-delay = <200>;
+ cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
+ status = "okay";
};
-&i2c1 {
+&mmuart1 {
status = "okay";
- clock-frequency = <100000>;
-
- pac193x: pac193x@10 {
- compatible = "microchip,pac1934";
- reg = <0x10>;
- samp-rate = <64>;
- status = "okay";
- ch1: channel0 {
- uohms-shunt-res = <10000>;
- rail-name = "VDDREG";
- channel_enabled;
- };
- ch2: channel1 {
- uohms-shunt-res = <10000>;
- rail-name = "VDDA25";
- channel_enabled;
- };
- ch3: channel2 {
- uohms-shunt-res = <10000>;
- rail-name = "VDD25";
- channel_enabled;
- };
- ch4: channel3 {
- uohms-shunt-res = <10000>;
- rail-name = "VDDA_REG";
- channel_enabled;
- };
- };
};
-&mac1 {
+&mmuart2 {
status = "okay";
- phy-mode = "sgmii";
- phy-handle = <&phy1>;
- phy1: ethernet-phy@9 {
- reg = <9>;
- ti,fifo-depth = <0x1>;
- };
+};
+
+&mmuart3 {
+ status = "okay";
+};
+
+&mmuart4 {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
};
&qspi {
status = "okay";
- num-cs = <1>;
+};
- flash0: flash@0 {
- compatible = "spi-nand";
- reg = <0x0>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <20000000>;
- spi-cpol;
- spi-cpha;
- };
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+ clock-frequency = <50000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
};