mmc: exynos_dw_mmc: Read and use DDR timing when available
DDR timing values should be defined in "samsung,dw-mshc-ddr-timing" dts
property, and used when DDR MMC mode is selected. Read that value from
dts and use it. If it's not available, use SDR timing values instead.
This change is following upstream Linux kernel implementation.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index b9d655c..32f3ea1 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -52,6 +52,7 @@
#endif
struct clk clk;
u32 sdr_timing;
+ u32 ddr_timing;
const struct exynos_dwmmc_variant *chip;
};
@@ -127,8 +128,14 @@
static int exynos_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+ u32 timing;
- dwmci_writel(host, priv->chip->clksel, priv->sdr_timing);
+ if (host->mmc->selected_mode == MMC_DDR_52)
+ timing = priv->ddr_timing;
+ else
+ timing = priv->sdr_timing;
+
+ dwmci_writel(host, priv->chip->clksel, timing);
return 0;
}
@@ -305,6 +312,17 @@
priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
}
+ err = dev_read_u32_array(dev, "samsung,dw-mshc-ddr-timing", timing, 2);
+ if (err) {
+ debug("DWMMC%d: Can't get ddr-timings, using sdr-timings\n",
+ host->dev_index);
+ priv->ddr_timing = priv->sdr_timing;
+ } else {
+ priv->ddr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) |
+ DWMCI_SET_DRV_CLK(timing[1]) |
+ DWMCI_SET_DIV_RATIO(div);
+ }
+
host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
host->bus_hz = dev_read_u32_default(dev, "clock-frequency", 0);