riscv: cache: Implement i/dcache [status, enable, disable]
AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.
This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.
This approach also provide the expansion when the
vender specific features are going to join in.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index d642a38..ae5c607 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -6,8 +6,18 @@
#include <common.h>
+void invalidate_icache_all(void)
+{
+ asm volatile ("fence.i" ::: "memory");
+}
+
+void flush_dcache_all(void)
+{
+ asm volatile ("fence" :::"memory");
+}
void flush_dcache_range(unsigned long start, unsigned long end)
{
+ flush_dcache_all();
}
void invalidate_icache_range(unsigned long start, unsigned long end)
@@ -19,41 +29,45 @@
invalidate_icache_all();
}
-void invalidate_icache_all(void)
-{
- asm volatile ("fence.i" ::: "memory");
-}
-
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
+ flush_dcache_all();
+}
+
+void cache_flush(void)
+{
+ invalidate_icache_all();
+ flush_dcache_all();
}
void flush_cache(unsigned long addr, unsigned long size)
{
+ invalidate_icache_all();
+ flush_dcache_all();
}
-void icache_enable(void)
+__weak void icache_enable(void)
{
}
-void icache_disable(void)
+__weak void icache_disable(void)
{
}
-int icache_status(void)
+__weak int icache_status(void)
{
return 0;
}
-void dcache_enable(void)
+__weak void dcache_enable(void)
{
}
-void dcache_disable(void)
+__weak void dcache_disable(void)
{
}
-int dcache_status(void)
+__weak int dcache_status(void)
{
return 0;
}