ddr: vybrid: Provide code to perform on-boot calibration
This patch provides the code to calibrate the DDR's
DQS to DQ signals (RDLVL).
It is based on:
VFxxx Controller Reference Manual, Rev. 0, 10/2016, page 1600
10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode"
and NXP's community thread:
"Vybrid: About DDR leveling feature on DDRMC."
https://community.nxp.com/thread/395323
Signed-off-by: Lukasz Majewski <lukma@denx.de>
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a1566cc..8631fbd 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -78,3 +78,15 @@
NXP boards based on i.MX6/7 contain the board revision information
stored in the fuses. Select this option if you want to be able to
retrieve the board revision information.
+
+config DDRMC_VF610_CALIBRATION
+ bool "Enable DDRMC (DDR3) on-chip calibration"
+ depends on ARCH_VF610
+ help
+ Vybrid (vf610) SoC provides some on-chip facility to tune the DDR3
+ memory parameters. Select this option if you want to calculate them
+ at boot time.
+ NOTE:
+ NXP does NOT recommend to perform this calibration at each boot. One
+ shall perform it on a new PCB and then use those values to program
+ the ddrmc_cr_setting on relevant board file.