| commit | 494d43ec35ff3d27926ed9d668e0df4b7e6ae6d3 | [log] [tgz] |
|---|---|---|
| author | Akshay Bhat <akshay.bhat@timesys.com> | Tue Apr 12 18:13:58 2016 -0400 |
| committer | Stefano Babic <sbabic@denx.de> | Tue Apr 19 16:05:13 2016 +0200 |
| tree | e1462a832210defa82bfad1e6bfaea86a7c2eb74 | |
| parent | de708da0e87f39d99f902a5434702d6ba0f4c5e0 [diff] |
board: ge: bx50v3: Setup LDB_DI_CLK source To generate accurate pixel clocks required by the displays we need to set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since PLL5 is disabled on reset, we need to enable PLL5. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>