| commit | 6c70935d7525a4b2b144b49457d2bae85f1d111a | [log] [tgz] |
|---|---|---|
| author | SRICHARAN R <r.sricharan@ti.com> | Fri Nov 08 17:40:37 2013 +0530 |
| committer | Tom Rini <trini@ti.com> | Wed Dec 04 08:12:08 2013 -0500 |
| tree | 663b91f30c048968bcef5a4bf3916b123c51f7ab | |
| parent | 39302dcd3013134e936cc76ccee8d1ed5522bfa0 [diff] |
ARM: DRA: EMIF: Change DDR3 settings to use hw leveling Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: Sricharan R <r.sricharan@ti.com>