Merge tag 'u-boot-dfu-20231103' of https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20231103
- Fix CRC chunk size in fastboot
- Make size optional for dfu on mmc
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index eb9353f..d6f3fa4 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -203,12 +203,12 @@
grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
- wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
- export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+ wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
+ export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
- wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
- export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+ wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
+ export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
# the below corresponds to .gitlab-ci.yml "script"
cd \${WORK_DIR}
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 1e11b5a..fee1651 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -32,12 +32,12 @@
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
- wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
- export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+ wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
+ export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
- wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
- export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+ wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
+ export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
after_script:
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 19a9e11..4f0adb0 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -118,6 +118,8 @@
#define HCR_EL2_E2H_BIT 34
#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
asm volatile("dsb sy");
diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-rmobile/board.c
index a10371f..79c7e02 100644
--- a/arch/arm/mach-rmobile/board.c
+++ b/arch/arm/mach-rmobile/board.c
@@ -3,7 +3,7 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
-#include <common.h>
+
#include <init.h>
#include <asm/io.h>
diff --git a/arch/arm/mach-rmobile/cpu_info-r8a7740.c b/arch/arm/mach-rmobile/cpu_info-r8a7740.c
index dcbe25f..5a94235 100644
--- a/arch/arm/mach-rmobile/cpu_info-r8a7740.c
+++ b/arch/arm/mach-rmobile/cpu_info-r8a7740.c
@@ -3,7 +3,7 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
-#include <common.h>
+
#include <asm/io.h>
u32 rmobile_get_cpu_type(void)
diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 8fc4cd7..b9d8b5e 100644
--- a/arch/arm/mach-rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
@@ -4,7 +4,7 @@
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*/
-#include <common.h>
+
#include <asm/io.h>
#define PRR_MASK 0x7fff
diff --git a/arch/arm/mach-rmobile/cpu_info-rzg.c b/arch/arm/mach-rmobile/cpu_info-rzg.c
index 1c18fd0..4ade4bc 100644
--- a/arch/arm/mach-rmobile/cpu_info-rzg.c
+++ b/arch/arm/mach-rmobile/cpu_info-rzg.c
@@ -3,7 +3,7 @@
* Copyright (C) 2021 Renesas Electronics Corporation
*
*/
-#include <common.h>
+
#include <linux/libfdt.h>
/* If the firmware passed a device tree, use it for soc identification. */
diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c b/arch/arm/mach-rmobile/cpu_info-rzg2l.c
index de4892e..f69649d 100644
--- a/arch/arm/mach-rmobile/cpu_info-rzg2l.c
+++ b/arch/arm/mach-rmobile/cpu_info-rzg2l.c
@@ -4,7 +4,6 @@
*
*/
-#include <common.h>
#include <asm/io.h>
#include <linux/libfdt.h>
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 6804b1d..895c0f5 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,7 +3,7 @@
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012-2021 Renesas Solutions Corp.
*/
-#include <common.h>
+
#include <cpu_func.h>
#include <asm/cache.h>
#include <init.h>
diff --git a/arch/arm/mach-rmobile/emac.c b/arch/arm/mach-rmobile/emac.c
index cb9bce0..9565162 100644
--- a/arch/arm/mach-rmobile/emac.c
+++ b/arch/arm/mach-rmobile/emac.c
@@ -6,7 +6,6 @@
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
*/
-#include <common.h>
#include <net.h>
#include <linux/errno.h>
#include <netdev.h>
diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c
index a68eb80..4dff9e0 100644
--- a/arch/arm/mach-rmobile/memmap-gen3.c
+++ b/arch/arm/mach-rmobile/memmap-gen3.c
@@ -5,10 +5,10 @@
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*/
-#include <common.h>
-#include <cpu_func.h>
#include <asm/armv8/mmu.h>
#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <cpu_func.h>
#define GEN3_NR_REGIONS 16
diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c b/arch/arm/mach-rmobile/memmap-rzg2l.c
index a08d0ea..9934a77 100644
--- a/arch/arm/mach-rmobile/memmap-rzg2l.c
+++ b/arch/arm/mach-rmobile/memmap-rzg2l.c
@@ -6,9 +6,9 @@
* Copyright (C) 2023 Renesas Electronics Corp.
*/
-#include <common.h>
#include <asm/armv8/mmu.h>
#include <asm/global_data.h>
+#include <asm/u-boot.h>
#include <cpu_func.h>
#define RZG2L_NR_REGIONS 16
diff --git a/arch/arm/mach-rmobile/pfc-r8a7740.c b/arch/arm/mach-rmobile/pfc-r8a7740.c
index 5d42a68..4f48476 100644
--- a/arch/arm/mach-rmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-rmobile/pfc-r8a7740.c
@@ -18,7 +18,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <common.h>
+
#include <sh_pfc.h>
#include <asm/gpio.h>
#include <asm/arch/irqs.h>
diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c b/arch/arm/mach-rmobile/psci-r8a779a0.c
index 6a85eb2..b6c49e7 100644
--- a/arch/arm/mach-rmobile/psci-r8a779a0.c
+++ b/arch/arm/mach-rmobile/psci-r8a779a0.c
@@ -6,7 +6,6 @@
*
*/
-#include <common.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8fc81fb..6d0d812 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,9 @@
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
+config TARGET_OPENPITON_RISCV64
+ bool "Support RISC-V cores on OpenPiton SoC"
+
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
@@ -24,6 +27,10 @@
bool "Support SiFive Unmatched Board"
select SYS_CACHE_SHIFT_6
+config TARGET_SIPEED_MAIX
+ bool "Support Sipeed Maix Board"
+ select SYS_CACHE_SHIFT_6
+
config TARGET_STARFIVE_VISIONFIVE2
bool "Support StarFive VisionFive2 Board"
select BOARD_LATE_INIT
@@ -32,13 +39,6 @@
bool "Support Sipeed's TH1520 Lichee PI 4A Board"
select SYS_CACHE_SHIFT_6
-config TARGET_SIPEED_MAIX
- bool "Support Sipeed Maix Board"
- select SYS_CACHE_SHIFT_6
-
-config TARGET_OPENPITON_RISCV64
- bool "Support RISC-V cores on OpenPiton SoC"
-
endchoice
config SYS_ICACHE_OFF
@@ -76,12 +76,12 @@
source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
+source "board/openpiton/riscv64/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
-source "board/thead/th1520_lpi4a/Kconfig"
-source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
source "board/starfive/visionfive2/Kconfig"
+source "board/thead/th1520_lpi4a/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index 6eb3ed1..5cad7b4 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -26,7 +26,7 @@
.text
/* trap entry */
- .align 2
+ .align 6
.global trap_entry
trap_entry:
addi sp, sp, -32 * REGBYTES
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a4..13c47f7 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -627,6 +627,16 @@
status = "disabled";
};
+ rng: rng@1600c000 {
+ compatible = "starfive,jh7110-trng";
+ reg = <0x0 0x1600C000 0x0 0x4000>;
+ clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+ <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+ clock-names = "hclk", "ahb";
+ resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+ interrupts = <30>;
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
new file mode 100644
index 0000000..90aa2f8
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: yanhong <yanhong.wang@starfivetech.com>
+ *
+ */
+
+#ifndef _GPIO_STARFIVE_H_
+#define _GPIO_STARFIVE_H_
+
+#include <asm/arch/regs.h>
+
+#define GPIO_NUM_SHIFT 2 /*one dword include 4 gpios*/
+#define GPIO_BYTE_SHIFT 3
+
+#define GPIO_INDEX_MASK 0x3
+
+#define GPIO_DOEN_MASK 0x3f
+#define GPIO_DOUT_MASK 0x7f
+#define GPIO_DIN_MASK 0x7f
+#define GPIO_DS_MASK 0x06
+#define GPIO_DS_SHIFT 1
+#define GPIO_SLEW_MASK BIT(5)
+#define GPIO_SLEW_SHIFT 5
+#define GPIO_PULL_MASK 0x18
+#define GPIO_PULL_SHIFT 3
+#define GPIO_PULL_UP 1
+#define GPIO_PULL_DOWN 2
+
+#define NR_GPIOS 64
+
+#define GPIO_OFFSET(gpio) \
+ (((gpio) >> GPIO_NUM_SHIFT) << GPIO_NUM_SHIFT)
+
+#define GPIO_SHIFT(gpio) \
+ (((gpio) & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT)
+
+enum gpio_state {
+ LOW,
+ HIGH
+};
+
+#define GPIO_DOEN 0x0
+#define GPIO_DOUT 0x40
+#define GPIO_DIN 0x80
+#define GPIO_EN 0xdc
+#define GPIO_LOW_IE 0x100
+#define GPIO_HIGH_IE 0x104
+#define GPIO_CONFIG 0x120
+
+#define SYS_IOMUX_DOEN(gpio, oen) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_OFFSET(gpio), \
+ GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \
+ (oen) << GPIO_SHIFT(gpio))
+
+#define SYS_IOMUX_DOUT(gpio, gpo) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DOUT + GPIO_OFFSET(gpio), \
+ GPIO_DOUT_MASK << GPIO_SHIFT(gpio), \
+ ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio))
+
+#define SYS_IOMUX_DIN(gpio, gpi)\
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+ GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+ ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
+#define SYS_IOMUX_SET_DS(gpio, ds) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+ GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
+
+#define SYS_IOMUX_SET_SLEW(gpio, slew) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+ GPIO_SLEW_MASK, (slew) << GPIO_SLEW_SHIFT)
+
+#define SYS_IOMUX_SET_PULL(gpio, pull) \
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+ GPIO_PULL_MASK, (pull) << GPIO_PULL_SHIFT)
+
+#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) \
+ do { \
+ SYS_IOMUX_DOEN(gpio, oen); \
+ SYS_IOMUX_DOUT(gpio, gpo); \
+ SYS_IOMUX_DIN(gpio, gpi); \
+ } while (0)
+
+#endif /* _GPIO_STARFIVE_H_ */
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index b16e6df..4170877 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -323,6 +323,51 @@
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
+/*
+ * Unordered I/O memory access primitives. These are even more relaxed than
+ * the relaxed versions, as they don't even order accesses between successive
+ * operations to the I/O regions.
+ */
+#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
+#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
+
+#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
+#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
+#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
+
+#ifdef CONFIG_64BIT
+#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
+#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
+#endif
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses. These are defined to order the indicated access (either a read or
+ * write) with all other I/O memory accesses to the same peripheral. Since the
+ * platform specification defines that all I/O regions are strongly ordered on
+ * channel 0, no explicit fences are required to enforce this ordering.
+ */
+/* FIXME: These are now the same as asm-generic */
+#define __io_rbr() do {} while (0)
+#define __io_rar() do {} while (0)
+#define __io_rbw() do {} while (0)
+#define __io_raw() do {} while (0)
+
+#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
+#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
+#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
+
+#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
+#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
+#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
+
+#ifdef CONFIG_64BIT
+#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
+#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
+#endif
+
#include <asm-generic/io.h>
#endif /* __ASM_RISCV_IO_H */
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index c46b49e..afad7e1 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -19,7 +19,7 @@
{
}
-void invalidate_icache_range(unsigned long start, unsigned long end)
+__weak void invalidate_icache_range(unsigned long start, unsigned long end)
{
/*
* RISC-V does not have an instruction for invalidating parts of the
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 02dbcfd..a26ccc7 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -12,6 +12,7 @@
#include <linux/compat.h>
#include <efi_loader.h>
#include <hang.h>
+#include <interrupt.h>
#include <irq_func.h>
#include <asm/global_data.h>
#include <asm/ptrace.h>
@@ -21,6 +22,13 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct resume_data *resume;
+
+void set_resume(struct resume_data *data)
+{
+ resume = data;
+}
+
static void show_efi_loaded_images(uintptr_t epc)
{
efi_print_image_infos((void *)epc);
@@ -105,6 +113,11 @@
"Store/AMO page fault",
};
+ if (resume) {
+ resume->code = code;
+ longjmp(resume->jump, 1);
+ }
+
if (code < ARRAY_SIZE(exception_code))
printf("Unhandled exception: %s\n", exception_code[code]);
else
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 2d184c5..1d50991 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -2,7 +2,7 @@
# Copyright (c) 2011 The Chromium OS Authors.
PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE
-PLATFORM_CPPFLAGS += -fPIC
+PLATFORM_CPPFLAGS += -fPIC -ffunction-sections -fdata-sections
PLATFORM_LIBS += -lrt
SDL_CONFIG ?= sdl2-config
@@ -30,7 +30,7 @@
$(u-boot-main) \
$(u-boot-keep-syms-lto) \
-Wl,--no-whole-archive \
- $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
+ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -Wl,--gc-sections
cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
$(KBUILD_LDFLAGS:%=-Wl,%) \
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index ba8dee5..52f13af 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -15,7 +15,7 @@
_u_boot_sandbox_getopt : {
*(_u_boot_sandbox_getopt_start)
- *(_u_boot_sandbox_getopt)
+ KEEP(*(_u_boot_sandbox_getopt))
*(_u_boot_sandbox_getopt_end)
}
diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c
index e52e0a5..59e1a42 100644
--- a/board/nuvoton/arbel_evb/arbel_evb.c
+++ b/board/nuvoton/arbel_evb/arbel_evb.c
@@ -16,7 +16,7 @@
#define DRAM_1GB_SIZE 0x40000000ULL
#define DRAM_2GB_ECC_SIZE 0x70000000ULL
#define DRAM_2GB_SIZE 0x80000000ULL
-#define DRAM_4GB_ECC_SIZE 0xE00000000ULL
+#define DRAM_4GB_ECC_SIZE 0xE0000000ULL
#define DRAM_4GB_SIZE 0x100000000ULL
DECLARE_GLOBAL_DATA_PTR;
@@ -29,7 +29,6 @@
int dram_init(void)
{
struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
- uint64_t delta = 0ULL;
/*
* get dram active size value from bootblock.
@@ -38,17 +37,21 @@
*/
gd->ram_size = readl(&gcr->scrpad_c);
- debug("%s: scrpad_c: %llx ", __func__, gd->ram_size);
- if (gd->ram_size == 0) {
+ if (gd->ram_size == 0)
gd->ram_size = readl(&gcr->scrpad_b);
- debug("%s: scrpad_b: %llx ", __func__, gd->ram_size);
- } else {
+ else
gd->ram_size *= 0x100000ULL;
- }
+
+ debug("ram_size: %llx ", gd->ram_size);
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
gd->bd->bi_dram[0].start = 0;
- debug("ram_size: %llx ", gd->ram_size);
switch (gd->ram_size) {
case DRAM_512MB_ECC_SIZE:
@@ -62,32 +65,28 @@
gd->bd->bi_dram[1].size = 0;
break;
case DRAM_4GB_ECC_SIZE:
- gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE;
+ gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
- gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
- delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE;
+ gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
+ (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
+ /* use bank0 only */
+ gd->ram_size = DRAM_2GB_SIZE;
break;
case DRAM_4GB_SIZE:
gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
- delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE;
+ /* use bank0 only */
+ gd->ram_size = DRAM_2GB_SIZE;
break;
default:
gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
+ gd->ram_size = DRAM_1GB_SIZE;
break;
}
- gd->ram_size -= delta;
-
return 0;
}
-int dram_init_banksize(void)
-{
- dram_init();
-
- return 0;
-}
diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
index 755747e..73201a8 100644
--- a/board/renesas/rzg2l/rzg2l.c
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -4,7 +4,6 @@
* Copyright (C) 2023 Renesas Electronics Corporation
*/
-#include <common.h>
#include <fdtdec.h>
#include <linux/libfdt.h>
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index ad5f71a..336f0cd 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/arch/eeprom.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/regs.h>
#include <asm/arch/spl.h>
#include <asm/io.h>
@@ -172,10 +173,32 @@
/* Update the memory size which read form eeprom or DT */
fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
}
+
+static void jh7110_jtag_init(void)
+{
+ /* nTRST: GPIO36 */
+ SYS_IOMUX_DOEN(36, HIGH);
+ SYS_IOMUX_DIN(36, 4);
+ /* TDI: GPIO61 */
+ SYS_IOMUX_DOEN(61, HIGH);
+ SYS_IOMUX_DIN(61, 19);
+ /* TMS: GPIO63 */
+ SYS_IOMUX_DOEN(63, HIGH);
+ SYS_IOMUX_DIN(63, 20);
+ /* TCK: GPIO60 */
+ SYS_IOMUX_DOEN(60, HIGH);
+ SYS_IOMUX_DIN(60, 29);
+ /* TDO: GPIO44 */
+ SYS_IOMUX_DOEN(44, 8);
+ SYS_IOMUX_DOUT(44, 22);
+}
+
int spl_board_init_f(void)
{
int ret;
+ jh7110_jtag_init();
+
ret = spl_soc_init();
if (ret) {
debug("JH7110 SPL init failed: %d\n", ret);
diff --git a/boot/bootflow.c b/boot/bootflow.c
index be543c8..6922e7e 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -752,7 +752,7 @@
in_quote = false;
continue;
}
- if (*p == '=') {
+ if (*p == '=' && !arg_end) {
arg_end = p;
val = p + 1;
} else if (*p == '"') {
@@ -788,7 +788,8 @@
}
/* if this is the target arg, update it */
- if (!strncmp(from, set_arg, arg_end - from)) {
+ if (arg_end - from == set_arg_len &&
+ !strncmp(from, set_arg, set_arg_len)) {
if (!buf) {
bool has_quote = val_end[-1] == '"';
diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c
index 20e0b1e..cd72db8 100644
--- a/boot/bootmeth_cros.c
+++ b/boot/bootmeth_cros.c
@@ -406,7 +406,7 @@
return -ENOSYS;
}
-#if CONFIG_IS_ENABLED(BOOSTD_FULL)
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
static int cros_read_all(struct udevice *dev, struct bootflow *bflow)
{
int ret;
@@ -419,7 +419,7 @@
return 0;
}
-#endif /* BOOSTD_FULL */
+#endif /* BOOTSTD_FULL */
static int cros_boot(struct udevice *dev, struct bootflow *bflow)
{
@@ -458,9 +458,9 @@
.read_bootflow = cros_read_bootflow,
.read_file = cros_read_file,
.boot = cros_boot,
-#if CONFIG_IS_ENABLED(BOOSTD_FULL)
+#if CONFIG_IS_ENABLED(BOOTSTD_FULL)
.read_all = cros_read_all,
-#endif /* BOOSTD_FULL */
+#endif /* BOOTSTD_FULL */
};
static const struct udevice_id cros_bootmeth_ids[] = {
diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c
index e9d9734..e6c42d4 100644
--- a/boot/bootmeth_efi_mgr.c
+++ b/boot/bootmeth_efi_mgr.c
@@ -14,6 +14,8 @@
#include <bootmeth.h>
#include <command.h>
#include <dm.h>
+#include <efi_loader.h>
+#include <efi_variable.h>
/**
* struct efi_mgr_priv - private info for the efi-mgr driver
@@ -46,13 +48,26 @@
static int efi_mgr_read_bootflow(struct udevice *dev, struct bootflow *bflow)
{
struct efi_mgr_priv *priv = dev_get_priv(dev);
+ efi_status_t ret;
+ efi_uintn_t size;
+ u16 *bootorder;
if (priv->fake_dev) {
bflow->state = BOOTFLOWST_READY;
return 0;
}
- /* To be implemented */
+ ret = efi_init_obj_list();
+ if (ret)
+ return log_msg_ret("init", ret);
+
+ /* Enable this method if the "BootOrder" UEFI exists. */
+ bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid,
+ &size);
+ if (bootorder) {
+ bflow->state = BOOTFLOWST_READY;
+ return 0;
+ }
return -EINVAL;
}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 60aed2c..fd16c3a 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1313,6 +1313,13 @@
on a eMMC device. The feature is optionally available on eMMC devices
conforming to standard >= 4.41.
+config CMD_MMC_REG
+ bool "Enable support for reading card registers in the mmc command"
+ depends on CMD_MMC
+ help
+ Enable the commands for reading card registers. This is useful
+ mostly for debugging or extracting details from the card.
+
config CMD_MMC_RPMB
bool "Enable support for RPMB in the mmc command"
depends on SUPPORT_EMMC_RPMB
diff --git a/cmd/cbfs.c b/cmd/cbfs.c
index 8a61f2c..3cfc9eb 100644
--- a/cmd/cbfs.c
+++ b/cmd/cbfs.c
@@ -118,7 +118,7 @@
case CBFS_TYPE_CBFSHEADER:
type_name = "cbfs header";
break;
- case CBFS_TYPE_STAGE:
+ case CBFS_TYPE_LEGACY_STAGE:
type_name = "stage";
break;
case CBFS_TYPE_PAYLOAD:
diff --git a/cmd/mmc.c b/cmd/mmc.c
index c6bd81c..96befb2 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -1110,6 +1110,93 @@
return CMD_RET_SUCCESS;
}
+#if CONFIG_IS_ENABLED(CMD_MMC_REG)
+static int do_mmc_reg(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+ struct mmc *mmc;
+ int i, ret;
+ u32 off;
+
+ if (argc < 3 || argc > 5)
+ return CMD_RET_USAGE;
+
+ mmc = find_mmc_device(curr_device);
+ if (!mmc) {
+ printf("no mmc device at slot %x\n", curr_device);
+ return CMD_RET_FAILURE;
+ }
+
+ if (IS_SD(mmc)) {
+ printf("SD registers are not supported\n");
+ return CMD_RET_FAILURE;
+ }
+
+ off = simple_strtoul(argv[3], NULL, 10);
+ if (!strcmp(argv[2], "cid")) {
+ if (off > 3)
+ return CMD_RET_USAGE;
+ printf("CID[%i]: 0x%08x\n", off, mmc->cid[off]);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->cid[off]);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "csd")) {
+ if (off > 3)
+ return CMD_RET_USAGE;
+ printf("CSD[%i]: 0x%08x\n", off, mmc->csd[off]);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->csd[off]);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "dsr")) {
+ printf("DSR: 0x%08x\n", mmc->dsr);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->dsr);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "ocr")) {
+ printf("OCR: 0x%08x\n", mmc->ocr);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->ocr);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "rca")) {
+ printf("RCA: 0x%08x\n", mmc->rca);
+ if (argv[4])
+ env_set_hex(argv[4], mmc->rca);
+ return CMD_RET_SUCCESS;
+ }
+ if (!strcmp(argv[2], "extcsd") &&
+ mmc->version >= MMC_VERSION_4_41) {
+ ret = mmc_send_ext_csd(mmc, ext_csd);
+ if (ret)
+ return CMD_RET_FAILURE;
+ if (!strcmp(argv[3], "all")) {
+ /* Dump the entire register */
+ printf("EXT_CSD:");
+ for (i = 0; i < MMC_MAX_BLOCK_LEN; i++) {
+ if (!(i % 10))
+ printf("\n%03i: ", i);
+ printf(" %02x", ext_csd[i]);
+ }
+ printf("\n");
+ return CMD_RET_SUCCESS;
+ }
+ off = simple_strtoul(argv[3], NULL, 10);
+ if (off > 512)
+ return CMD_RET_USAGE;
+ printf("EXT_CSD[%i]: 0x%02x\n", off, ext_csd[off]);
+ if (argv[4])
+ env_set_hex(argv[4], ext_csd[off]);
+ return CMD_RET_SUCCESS;
+ }
+
+ return CMD_RET_FAILURE;
+}
+#endif
+
static struct cmd_tbl cmd_mmc[] = {
U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""),
U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""),
@@ -1142,6 +1229,9 @@
U_BOOT_CMD_MKENT(bkops-enable, 2, 0, do_mmc_bkops_enable, "", ""),
U_BOOT_CMD_MKENT(bkops, 4, 0, do_mmc_bkops, "", ""),
#endif
+#if CONFIG_IS_ENABLED(CMD_MMC_REG)
+ U_BOOT_CMD_MKENT(reg, 5, 0, do_mmc_reg, "", ""),
+#endif
};
static int do_mmcops(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -1230,6 +1320,12 @@
"mmc bkops <dev> [auto|manual] [enable|disable]\n"
" - configure background operations handshake on device\n"
#endif
+#if CONFIG_IS_ENABLED(CMD_MMC_REG)
+ "mmc reg read <reg> <offset> [env] - read card register <reg> offset <offset>\n"
+ " (optionally into [env] variable)\n"
+ " - reg: cid/csd/dsr/ocr/rca/extcsd\n"
+ " - offset: for cid/csd [0..3], for extcsd [0..511,all]\n"
+#endif
);
/* Old command kept for compatibility. Same as 'mmc info' */
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
index 8c32b4b..6cfb5a7 100644
--- a/configs/arbel_evb_defconfig
+++ b/configs/arbel_evb_defconfig
@@ -58,6 +58,7 @@
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 074936d..3cd6aa0 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -14,7 +14,7 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
-CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
+CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
CONFIG_CONSOLE_RECORD=y
CONFIG_LOGLEVEL=7
# CONFIG_DISPLAY_CPUINFO is not set
@@ -55,6 +55,7 @@
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index b21754f..b15e7d2 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -120,6 +120,8 @@
CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
CONFIG_PINCTRL_STARFIVE=y
# CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RNG=y
+CONFIG_RNG_JH7110=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_TIMER_EARLY=y
diff --git a/doc/api/index.rst b/doc/api/index.rst
index 2f0218c..51b2013 100644
--- a/doc/api/index.rst
+++ b/doc/api/index.rst
@@ -12,6 +12,7 @@
efi
event
getopt
+ interrupt
linker_lists
lmb
logging
diff --git a/doc/api/interrupt.rst b/doc/api/interrupt.rst
new file mode 100644
index 0000000..5721231
--- /dev/null
+++ b/doc/api/interrupt.rst
@@ -0,0 +1,6 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Interrupt API
+=============
+
+.. kernel-doc:: include/interrupt.h
diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst
index aa7080e..46712c3 100644
--- a/doc/board/socionext/developerbox.rst
+++ b/doc/board/socionext/developerbox.rst
@@ -42,9 +42,10 @@
You can build U-Boot without any additinal source code.::
cd u-boot
+ git checkout v2023.07
export ARCH=arm64
export CROSS_COMPILE=aarch64-linux-gnu-
- make SynQuacer_defconfig
+ make synquacer_developerbox_defconfig
make -j `noproc`
Then, expand the binary to 1MB for preparing flash.::
@@ -211,8 +212,8 @@
Once the flasher tool is running we are ready to flash the images.::
Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.::
- flash rawwrite 600000 180000
- flash rawwrite a00000 180000
+ flash rawwrite 600000 400000
+ flash rawwrite a00000 400000
>> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) <<
flash rawwrite 500000 1000
diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst
index 71a0303..c0924ba 100644
--- a/doc/usage/cmd/mmc.rst
+++ b/doc/usage/cmd/mmc.rst
@@ -21,6 +21,7 @@
mmc bootpart-resize <dev> <dev part size MB> <RPMB part size MB>
mmc partconf <dev> [[varname] | [<boot_ack> <boot_partition> <partition_access>]]
mmc rst-function <dev> <value>
+ mmc reg read <reg> <offset> [env]
Description
-----------
@@ -183,6 +184,31 @@
0x3
Reserved
+The 'mmc reg read <reg> <offset> [env]' reads eMMC card register and
+either print it to standard output, or store the value in environment
+variable.
+
+<reg> with
+optional offset <offset> into the register array, and print it to
+standard output or store it into environment variable [env].
+
+ reg
+ cid
+ The Device IDentification (CID) register. Uses offset.
+ csd
+ The Device-Specific Data (CSD) register. Uses offset.
+ dsr
+ The driver stage register (DSR).
+ ocr
+ The operation conditions register (OCR).
+ rca
+ The relative Device address (RCA) register.
+ extcsd
+ The Extended CSD register. Uses offset.
+ offset
+ For 'cid'/'csd' 128 bit registers '[0..3]' in 32-bit increments. For 'extcsd' 512 bit register '[0..512,all]' in 8-bit increments, or 'all' to read the entire register.
+ env
+ Optional environment variable into which 32-bit value read from register should be stored.
Examples
--------
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 570252d..3c56253 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -79,14 +79,6 @@
Store the bootcount in DRAM protected against bit errors
due to short power loss or holding a system in RESET.
-config BOOTCOUNT_I2C
- bool "Boot counter on I2C device"
- help
- Enable support for the bootcounter on an i2c (like RTC) device.
- CFG_SYS_I2C_RTC_ADDR = i2c chip address
- CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
- the bootcounter.
-
config BOOTCOUNT_AT91
bool "Boot counter for Atmel AT91SAM9XE"
depends on AT91SAM9XE
@@ -117,6 +109,16 @@
Accesses to the backing store are performed using the write16
and read16 ops of DM RTC devices.
+config DM_BOOTCOUNT_I2C
+ bool "Driver Model boot counter on I2C device"
+ depends on DM_I2C
+ help
+ Enable support for the bootcounter on a generic i2c device, like a RTC
+ or PMIC. The bootcounter is configured in the device tree using the
+ "u-boot,bootcount-i2c" compatible string. It requires a phandle
+ 'i2cbcdev' for the i2c device and an 'offset' property used within the
+ device.
+
config DM_BOOTCOUNT_I2C_EEPROM
bool "Support i2c eeprom devices as a backing store for bootcount"
depends on I2C_EEPROM
@@ -175,14 +177,6 @@
counter being cleared.
If set to 0, do not set a boot limit in the environment.
-config BOOTCOUNT_ALEN
- int "I2C address length"
- default 1
- depends on BOOTCOUNT_I2C
- help
- Length of the the I2C address at SYS_BOOTCOUNT_ADDR for storing
- the boot counter.
-
config SYS_BOOTCOUNT_SINGLEWORD
bool "Use single word to pack boot count and magic value"
depends on BOOTCOUNT_GENERIC
@@ -218,7 +212,7 @@
default 0x44E3E000 if BOOTCOUNT_AM33XX || BOOTCOUNT_AM33XX_NVMEM
default 0xE0115FF8 if ARCH_LS1043A || ARCH_LS1021A
depends on BOOTCOUNT_AM33XX || BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
- BOOTCOUNT_I2C || BOOTCOUNT_AM33XX_NVMEM
+ BOOTCOUNT_AM33XX_NVMEM
help
Set the address used for reading and writing the boot counter.
@@ -226,13 +220,11 @@
hex "Magic value for the boot counter"
default 0xB001C041 if BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
BOOTCOUNT_AM33XX || BOOTCOUNT_ENV || \
- BOOTCOUNT_RAM || BOOTCOUNT_I2C || \
- BOOTCOUNT_AT91 || DM_BOOTCOUNT
+ BOOTCOUNT_RAM || BOOTCOUNT_AT91 || DM_BOOTCOUNT
default 0xB0 if BOOTCOUNT_AM33XX_NVMEM
depends on BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \
BOOTCOUNT_AM33XX || BOOTCOUNT_ENV || \
- BOOTCOUNT_RAM || BOOTCOUNT_I2C || \
- BOOTCOUNT_AT91 || DM_BOOTCOUNT || \
+ BOOTCOUNT_RAM || BOOTCOUNT_AT91 || DM_BOOTCOUNT || \
BOOTCOUNT_AM33XX_NVMEM
help
Set the magic value used for the boot counter.
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index b65959a..e7771f5 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -6,7 +6,6 @@
obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o
obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o
obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o
-obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o
obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o
obj-$(CONFIG_BOOTCOUNT_AM33XX_NVMEM) += bootcount_nvmem.o
@@ -14,5 +13,6 @@
obj-$(CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o
obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o
+obj-$(CONFIG_DM_BOOTCOUNT_I2C) += bootcount_dm_i2c.o
obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH) += spi-flash.o
obj-$(CONFIG_DM_BOOTCOUNT_SYSCON) += bootcount_syscon.o
diff --git a/drivers/bootcount/bootcount_dm_i2c.c b/drivers/bootcount/bootcount_dm_i2c.c
new file mode 100644
index 0000000..e27034c
--- /dev/null
+++ b/drivers/bootcount/bootcount_dm_i2c.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023
+ * Philip Richard Oberfichtner <pro@denx.de>
+ *
+ * Based on previous work from Heiko Schocher (legacy bootcount_i2c.c driver)
+ */
+
+#include <bootcount.h>
+#include <dm.h>
+#include <i2c.h>
+
+#define BC_MAGIC 0x55
+
+struct bootcount_i2c_priv {
+ struct udevice *bcdev;
+ unsigned int offset;
+};
+
+static int bootcount_i2c_set(struct udevice *dev, const u32 val)
+{
+ int ret;
+ struct bootcount_i2c_priv *priv = dev_get_priv(dev);
+
+ ret = dm_i2c_reg_write(priv->bcdev, priv->offset, BC_MAGIC);
+ if (ret < 0)
+ goto err_exit;
+
+ ret = dm_i2c_reg_write(priv->bcdev, priv->offset + 1, val & 0xff);
+ if (ret < 0)
+ goto err_exit;
+
+ return 0;
+
+err_exit:
+ log_debug("%s: Error writing to I2C device (%d)\n", __func__, ret);
+ return ret;
+}
+
+static int bootcount_i2c_get(struct udevice *dev, u32 *val)
+{
+ int ret;
+ struct bootcount_i2c_priv *priv = dev_get_priv(dev);
+
+ ret = dm_i2c_reg_read(priv->bcdev, priv->offset);
+ if (ret < 0)
+ goto err_exit;
+
+ if ((ret & 0xff) != BC_MAGIC) {
+ log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__);
+ *val = 0;
+ return bootcount_i2c_set(dev, 0);
+ }
+
+ ret = dm_i2c_reg_read(priv->bcdev, priv->offset + 1);
+ if (ret < 0)
+ goto err_exit;
+
+ *val = ret;
+ return 0;
+
+err_exit:
+ log_debug("%s: Error reading from I2C device (%d)\n", __func__, ret);
+ return ret;
+}
+
+static int bootcount_i2c_probe(struct udevice *dev)
+{
+ struct bootcount_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = dev_read_u32(dev, "offset", &priv->offset);
+ if (ret)
+ goto exit;
+
+ ret = i2c_get_chip_by_phandle(dev, "i2cbcdev", &priv->bcdev);
+
+exit:
+ if (ret)
+ log_debug("%s failed, ret = %d\n", __func__, ret);
+
+ return ret;
+}
+
+static const struct bootcount_ops bootcount_i2c_ops = {
+ .get = bootcount_i2c_get,
+ .set = bootcount_i2c_set,
+};
+
+static const struct udevice_id bootcount_i2c_ids[] = {
+ { .compatible = "u-boot,bootcount-i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(bootcount_i2c) = {
+ .name = "bootcount-i2c",
+ .id = UCLASS_BOOTCOUNT,
+ .priv_auto = sizeof(struct bootcount_i2c_priv),
+ .probe = bootcount_i2c_probe,
+ .of_match = bootcount_i2c_ids,
+ .ops = &bootcount_i2c_ops,
+};
diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c
deleted file mode 100644
index b3ac67e..0000000
--- a/drivers/bootcount/bootcount_i2c.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-
-#include <bootcount.h>
-#include <linux/compiler.h>
-#include <i2c.h>
-
-#define BC_MAGIC 0xbc
-
-void bootcount_store(ulong a)
-{
- unsigned char buf[3];
- int ret;
-
- buf[0] = BC_MAGIC;
- buf[1] = (a & 0xff);
- ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
- CONFIG_BOOTCOUNT_ALEN, buf, 2);
- if (ret != 0)
- puts("Error writing bootcount\n");
-}
-
-ulong bootcount_load(void)
-{
- unsigned char buf[3];
- int ret;
-
- ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
- CONFIG_BOOTCOUNT_ALEN, buf, 2);
- if (ret != 0) {
- puts("Error loading bootcount\n");
- return 0;
- }
- if (buf[0] == BC_MAGIC)
- return buf[1];
-
- bootcount_store(0);
-
- return 0;
-}
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index f186fcb..3b5e3f9 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -422,12 +422,13 @@
return clk_get_by_index_nodev(node, index, clk);
}
-int clk_release_all(struct clk *clk, int count)
+int clk_release_all(struct clk *clk, unsigned int count)
{
- int i, ret;
+ unsigned int i;
+ int ret;
for (i = 0; i < count; i++) {
- debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
+ debug("%s(clk[%u]=%p)\n", __func__, i, &clk[i]);
/* check if clock has been previously requested */
if (!clk[i].dev)
@@ -477,7 +478,7 @@
ulong clk_get_rate(struct clk *clk)
{
const struct clk_ops *ops;
- int ret;
+ ulong ret;
debug("%s(clk=%p)\n", __func__, clk);
if (!clk_valid(clk))
@@ -655,7 +656,7 @@
}
if (ops->enable) {
- ret = ops->enable(clk);
+ ret = ops->enable(clkp ? clkp : clk);
if (ret) {
printf("Enable %s failed\n", clk->dev->name);
return ret;
@@ -712,7 +713,7 @@
}
if (ops->disable) {
- ret = ops->disable(clk);
+ ret = ops->disable(clkp ? clkp : clk);
if (ret)
return ret;
}
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 2336028..c8baad1 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -5,7 +5,6 @@
* Copyright (C) 2021-2023 Renesas Electronics Corp.
*/
-#include <common.h>
#include <dm/device.h>
#include <dt-bindings/clock/r9a07g044-cpg.h>
#include <linux/clk-provider.h>
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3295ebb..e54508c 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -11,7 +11,6 @@
* Copyright (C) 2015 Renesas Electronics Corp.
*/
-#include <common.h>
#include <asm/io.h>
#include <clk-uclass.h>
#include <dm.h>
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index 31aaf33..a835541 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -539,6 +539,16 @@
"pcie1_tl", "stg_axiahb",
OFFSET(JH7110_STGCLK_PCIE1_TL)));
+ /* Security clocks */
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+ starfive_clk_gate(priv->reg,
+ "sec_ahb", "stg_axiahb",
+ OFFSET(JH7110_STGCLK_SEC_HCLK)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+ starfive_clk_gate(priv->reg,
+ "sec_misc_ahb", "stg_axiahb",
+ OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+
return 0;
}
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
index bf762c5..c1158c1 100644
--- a/drivers/clk/ti/clk-k3-pll.c
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -25,6 +25,23 @@
#define PLL_16FFT_FREQ_CTRL0 0x30
#define PLL_16FFT_FREQ_CTRL1 0x34
#define PLL_16FFT_DIV_CTRL 0x38
+#define PLL_16FFT_CAL_CTRL 0x60
+#define PLL_16FFT_CAL_STAT 0x64
+
+/* CAL STAT register bits */
+#define PLL_16FFT_CAL_STAT_CAL_LOCK BIT(31)
+
+/* CFG register bits */
+#define PLL_16FFT_CFG_PLL_TYPE_SHIFT (0)
+#define PLL_16FFT_CFG_PLL_TYPE_MASK (0x3 << 0)
+#define PLL_16FFT_CFG_PLL_TYPE_FRACF 1
+
+/* CAL CTRL register bits */
+#define PLL_16FFT_CAL_CTRL_CAL_EN BIT(31)
+#define PLL_16FFT_CAL_CTRL_FAST_CAL BIT(20)
+#define PLL_16FFT_CAL_CTRL_CAL_BYP BIT(15)
+#define PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT 16
+#define PLL_16FFT_CAL_CTRL_CAL_CNT_MASK (0x7 << 16)
/* CTRL register bits */
#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
@@ -40,9 +57,14 @@
/* DIV CTRL register bits */
#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f
-#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
+/* HSDIV register bits*/
#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15)
+/* FREQ_CTRL1 bits */
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK 0xffffff
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT 0
+
/* KICK register magic values */
#define PLL_KICK0_VALUE 0x68ef3490
#define PLL_KICK1_VALUE 0xd172bc5a
@@ -63,18 +85,65 @@
{
struct ti_pll_clk *pll = to_clk_pll(clk);
u32 stat;
+ u32 cfg;
+ u32 cal;
+ u32 freq_ctrl1;
int i;
+ u32 pllfm;
+ u32 pll_type;
+ int success;
for (i = 0; i < 100000; i++) {
stat = readl(pll->reg + PLL_16FFT_STAT);
- if (stat & PLL_16FFT_STAT_LOCK)
- return 0;
+ if (stat & PLL_16FFT_STAT_LOCK) {
+ success = 1;
+ break;
+ }
}
- printf("%s: pll (%s) failed to lock\n", __func__,
- clk->dev->name);
+ /* Enable calibration if not in fractional mode of the FRACF PLL */
+ freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+ pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK;
+ pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT;
+ cfg = readl(pll->reg + PLL_16FFT_CFG);
+ pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT;
- return -EBUSY;
+ if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) {
+ cal = readl(pll->reg + PLL_16FFT_CAL_CTRL);
+
+ /* Enable calibration for FRACF */
+ cal |= PLL_16FFT_CAL_CTRL_CAL_EN;
+
+ /* Enable fast cal mode */
+ cal |= PLL_16FFT_CAL_CTRL_FAST_CAL;
+
+ /* Disable calibration bypass */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP;
+
+ /* Set CALCNT to 2 */
+ cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK;
+ cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT;
+
+ /* Note this register does not readback the written value. */
+ writel(cal, pll->reg + PLL_16FFT_CAL_CTRL);
+
+ success = 0;
+ for (i = 0; i < 100000; i++) {
+ stat = readl(pll->reg + PLL_16FFT_CAL_STAT);
+ if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) {
+ success = 1;
+ break;
+ }
+ }
+ }
+
+ if (success == 0) {
+ printf("%s: pll (%s) failed to lock\n", __func__,
+ clk->dev->name);
+ return -EBUSY;
+ } else {
+ return 0;
+ }
}
static ulong ti_pll_clk_get_rate(struct clk *clk)
diff --git a/drivers/gpio/rzg2l-gpio.c b/drivers/gpio/rzg2l-gpio.c
index 7c908d0..2477af7 100644
--- a/drivers/gpio/rzg2l-gpio.c
+++ b/drivers/gpio/rzg2l-gpio.c
@@ -5,7 +5,6 @@
* Copyright (C) 2021-2023 Renesas Electronics Corp.
*/
-#include <common.h>
#include <asm-generic/gpio.h>
#include <asm/io.h>
#include <dm/device.h>
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index e54de42..215ce01 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -24,6 +24,17 @@
*/
#define DW_I2C_COMP_TYPE 0x44570140
+/*
+ * This constant is used to calculate when during the clock high phase the data
+ * bit shall be read. The value was copied from the Linux v6.5 function
+ * i2c_dw_scl_hcnt() which provides the following explanation:
+ *
+ * "This is just an experimental rule: the tHD;STA period turned out to be
+ * proportinal to (_HCNT + 3). With this setting, we could meet both tHIGH and
+ * tHD;STA timing specs."
+ */
+#define T_HD_STA_OFFSET 3
+
static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
u32 ena = enable ? IC_ENABLE_0B : 0;
@@ -155,10 +166,10 @@
/*
* Back-solve for hcnt and lcnt according to the following equations:
- * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
+ * SCL_High_time = [(HCNT + IC_*_SPKLEN + T_HD_STA_OFFSET) * ic_clk] + SCL_Fall_time
* SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
*/
- hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
+ hcnt = min_thigh_cnt - fall_cnt - T_HD_STA_OFFSET - spk_cnt;
lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
if (hcnt < 0 || lcnt < 0) {
@@ -170,13 +181,13 @@
* Now add things back up to ensure the period is hit. If it is off,
* split the difference and bias to lcnt for remainder
*/
- tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
+ tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1;
if (tot < period_cnt) {
diff = (period_cnt - tot) / 2;
hcnt += diff;
lcnt += diff;
- tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
+ tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1;
lcnt += period_cnt - tot;
}
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 8867a56..5405067 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -388,6 +388,81 @@
return 0;
}
+/* Find and probe I2C bus based on a chip attached to it */
+static int i2c_get_parent_bus(ofnode chip, struct udevice **devp)
+{
+ ofnode node;
+ struct udevice *dev;
+ int ret;
+
+ node = ofnode_get_parent(chip);
+ if (!ofnode_valid(node))
+ return -ENODEV;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_I2C, node, &dev);
+ if (ret) {
+ *devp = NULL;
+ return ret;
+ }
+
+ *devp = dev;
+ return 0;
+}
+
+int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name,
+ struct udevice **devp)
+{
+ ofnode node;
+ uint phandle;
+ struct udevice *bus, *chip;
+ char *dev_name;
+ int ret;
+
+ debug("%s: Searching I2C chip for phandle \"%s\"\n",
+ __func__, prop_name);
+
+ dev_name = strdup(prop_name);
+ if (!dev_name) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ ret = dev_read_u32(parent, "i2cbcdev", &phandle);
+ if (ret)
+ goto err_exit;
+
+ node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(node)) {
+ ret = -ENODEV;
+ goto err_exit;
+ }
+
+ ret = i2c_get_parent_bus(node, &bus);
+ if (ret)
+ goto err_exit;
+
+ ret = device_bind_driver_to_node(bus, "i2c_generic_chip_drv",
+ dev_name, node, &chip);
+ if (ret)
+ goto err_exit;
+
+ ret = device_probe(chip);
+ if (ret) {
+ device_unbind(chip);
+ goto err_exit;
+ }
+
+ debug("%s succeeded\n", __func__);
+ *devp = chip;
+ return 0;
+
+err_exit:
+ free(dev_name);
+ debug("%s failed, ret = %d\n", __func__, ret);
+ *devp = NULL;
+ return ret;
+}
+
int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
struct udevice **devp)
{
diff --git a/drivers/i2c/npcm_i2c.c b/drivers/i2c/npcm_i2c.c
index ea4ef53..b867b6c 100644
--- a/drivers/i2c/npcm_i2c.c
+++ b/drivers/i2c/npcm_i2c.c
@@ -517,11 +517,6 @@
u32 sclfrq;
u8 hldt, val;
- if (bus_freq > I2C_FREQ_100K) {
- printf("Support standard mode only\n");
- return -EINVAL;
- }
-
/* SCLFRQ = T(SCL)/4/T(CLK) = FREQ(CLK)/4/FREQ(SCL) */
sclfrq = freq / (bus_freq * 4);
if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 001f0a8..591ff30 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -151,7 +151,7 @@
/* Response code is first byte of message */
if (p[0] != EC_RES_SUCCESS) {
- printf("%s: Returned status %d\n", __func__, p[0]);
+ log_debug("Returned status %d\n", p[0]);
return -(int)(p[0]);
}
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 726c8d8..17618c3 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -46,6 +46,7 @@
depends on SPL_DM && DM_MMC
default n if ARCH_MVEBU && !MVEBU_SPL_BOOT_DEVICE_MMC
default y
+ select SPL_BLK
help
This enables the MultiMediaCard (MMC) uclass which supports MMC and
Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index 9fb7044..4d163cc 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -50,8 +50,8 @@
desc = mmc_get_blk_desc(&plat->mmc);
desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE);
- host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
- PCI_REGION_MEM);
+ host->ioaddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
+ PCI_REGION_TYPE, PCI_REGION_MEM);
host->name = dev->name;
host->cd_gpio = priv->cd_gpio;
host->mmc = &plat->mmc;
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 865efdd..8cd501c 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -3,7 +3,6 @@
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
-#include <common.h>
#include <bouncebuf.h>
#include <clk.h>
#include <fdtdec.h>
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index fc9c6c3..0178ed8 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -306,14 +306,19 @@
if (stat & SDHCI_INT_ERROR)
break;
- if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
- if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
+ if (host->quirks & SDHCI_QUIRK_BROKEN_R1B &&
+ cmd->resp_type & MMC_RSP_BUSY && !data) {
+ unsigned int state =
+ sdhci_readl(host, SDHCI_PRESENT_STATE);
+
+ if (!(state & SDHCI_DAT_ACTIVE))
return 0;
- } else {
- printf("%s: Timeout for status update!\n",
- __func__);
- return -ETIMEDOUT;
- }
+ }
+
+ if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
+ printf("%s: Timeout for status update: %08x %08x\n",
+ __func__, stat, mask);
+ return -ETIMEDOUT;
}
} while ((stat & mask) != mask);
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 76c424d..2b2efc8 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -82,6 +82,7 @@
config BOOTDEV_SPI_FLASH
bool "SPI Flash bootdev support"
+ depends on BOOTSTD
help
Enable a boot device for SPI flash. This allows reading a script
from SPI flash so that it can be used to boot an Operating System.
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index 7976e3b..ff49819 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -329,6 +329,7 @@
static const struct group_info npcm8xx_groups[] = {
FUNC_LIST
+ {FN_gpio, "GPIO", NULL, 0, 0, 0}
};
/* Pin flags */
diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c
index 7b045f7..e88ec1c 100644
--- a/drivers/pinctrl/renesas/rzg2l-pfc.c
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -5,7 +5,6 @@
* Copyright (C) 2021-2023 Renesas Electronics Corp.
*/
-#include <common.h>
#include <asm/io.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 994cc35..a89c899 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -48,6 +48,14 @@
accessible to normal world but reserved and used by the OP-TEE
to avoid the weakness of a software PRNG.
+config RNG_RISCV_ZKR
+ bool "RISC-V Zkr random number generator"
+ depends on RISCV_SMODE
+ help
+ This driver provides a Random Number Generator based on the
+ Zkr RISC-V ISA extension which provides an interface to an
+ NIST SP 800-90B or BSI AIS-31 compliant physical entropy source.
+
config RNG_STM32
bool "Enable random number generator for STM32"
depends on ARCH_STM32 || ARCH_STM32MP
@@ -91,4 +99,10 @@
functionality. Enable random number generator on TPM
devices.
+config RNG_JH7110
+ bool "StarFive JH7110 Random Number Generator support"
+ depends on DM_RNG && STARFIVE_JH7110
+ help
+ Enable True Random Number Generator in StarFive JH7110 SoCs.
+
endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 47b323e..7e64c4c 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -10,8 +10,10 @@
obj-$(CONFIG_RNG_NPCM) += npcm_rng.o
obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
obj-$(CONFIG_RNG_STM32) += stm32_rng.o
+obj-$(CONFIG_RNG_RISCV_ZKR) += riscv_zkr_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
obj-$(CONFIG_TPM_RNG) += tpm_rng.o
+obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
new file mode 100644
index 0000000..eb21afe
--- /dev/null
+++ b/drivers/rng/jh7110_rng.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * TRNG driver for the StarFive JH7110 SoC
+ *
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <reset.h>
+#include <rng.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+
+/* trng register offset */
+#define STARFIVE_CTRL 0x00
+#define STARFIVE_STAT 0x04
+#define STARFIVE_MODE 0x08
+#define STARFIVE_SMODE 0x0C
+#define STARFIVE_IE 0x10
+#define STARFIVE_ISTAT 0x14
+#define STARFIVE_RAND0 0x20
+#define STARFIVE_RAND1 0x24
+#define STARFIVE_RAND2 0x28
+#define STARFIVE_RAND3 0x2C
+#define STARFIVE_RAND4 0x30
+#define STARFIVE_RAND5 0x34
+#define STARFIVE_RAND6 0x38
+#define STARFIVE_RAND7 0x3C
+#define STARFIVE_AUTO_RQSTS 0x60
+#define STARFIVE_AUTO_AGE 0x64
+
+/* CTRL CMD */
+#define STARFIVE_CTRL_EXEC_NOP 0x0
+#define STARFIVE_CTRL_GENE_RANDNUM 0x1
+#define STARFIVE_CTRL_EXEC_RANDRESEED 0x2
+
+/* STAT */
+#define STARFIVE_STAT_NONCE_MODE BIT(2)
+#define STARFIVE_STAT_R256 BIT(3)
+#define STARFIVE_STAT_MISSION_MODE BIT(8)
+#define STARFIVE_STAT_SEEDED BIT(9)
+#define STARFIVE_STAT_LAST_RESEED(x) ((x) << 16)
+#define STARFIVE_STAT_SRVC_RQST BIT(27)
+#define STARFIVE_STAT_RAND_GENERATING BIT(30)
+#define STARFIVE_STAT_RAND_SEEDING BIT(31)
+#define STARFIVE_STAT_RUNNING (STARFIVE_STAT_RAND_GENERATING | \
+ STARFIVE_STAT_RAND_SEEDING)
+
+/* MODE */
+#define STARFIVE_MODE_R256 BIT(3)
+
+/* SMODE */
+#define STARFIVE_SMODE_NONCE_MODE BIT(2)
+#define STARFIVE_SMODE_MISSION_MODE BIT(8)
+#define STARFIVE_SMODE_MAX_REJECTS(x) ((x) << 16)
+
+/* IE */
+#define STARFIVE_IE_RAND_RDY_EN BIT(0)
+#define STARFIVE_IE_SEED_DONE_EN BIT(1)
+#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
+#define STARFIVE_IE_GLBL_EN BIT(31)
+
+#define STARFIVE_IE_ALL (STARFIVE_IE_GLBL_EN | \
+ STARFIVE_IE_RAND_RDY_EN | \
+ STARFIVE_IE_SEED_DONE_EN | \
+ STARFIVE_IE_LFSR_LOCKUP_EN)
+
+/* ISTAT */
+#define STARFIVE_ISTAT_RAND_RDY BIT(0)
+#define STARFIVE_ISTAT_SEED_DONE BIT(1)
+#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
+
+#define STARFIVE_RAND_LEN sizeof(u32)
+
+enum mode {
+ PRNG_128BIT,
+ PRNG_256BIT,
+};
+
+struct starfive_trng_plat {
+ void *base;
+ struct clk *hclk;
+ struct clk *ahb;
+ struct reset_ctl *rst;
+ u32 mode;
+};
+
+static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng)
+{
+ u32 stat;
+
+ return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
+ !(stat & STARFIVE_STAT_RUNNING),
+ 100000);
+}
+
+static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat *trng)
+{
+ /* clear register: ISTAT */
+ u32 data = readl(trng->base + STARFIVE_ISTAT);
+
+ writel(data, trng->base + STARFIVE_ISTAT);
+}
+
+static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
+{
+ u32 stat, flg;
+ int ret;
+
+ switch (cmd) {
+ case STARFIVE_CTRL_GENE_RANDNUM:
+ writel(cmd, trng->base + STARFIVE_CTRL);
+ flg = STARFIVE_ISTAT_RAND_RDY;
+ break;
+ case STARFIVE_CTRL_EXEC_RANDRESEED:
+ writel(cmd, trng->base + STARFIVE_CTRL);
+ flg = STARFIVE_ISTAT_SEED_DONE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = readl_relaxed_poll_timeout(trng->base + STARFIVE_ISTAT, stat,
+ (stat & flg), 1000);
+ writel(flg, trng->base + STARFIVE_ISTAT);
+
+ return ret;
+}
+
+static int starfive_trng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct starfive_trng_plat *trng = dev_get_plat(dev);
+ u8 *buffer = data;
+ int iter_mask;
+
+ if (trng->mode == PRNG_256BIT)
+ iter_mask = 7;
+ else
+ iter_mask = 3;
+
+ for (int i = 0; len; ++i, i &= iter_mask) {
+ u32 val;
+ size_t step;
+ int ret;
+
+ if (!i) {
+ ret = starfive_trng_cmd(trng,
+ STARFIVE_CTRL_GENE_RANDNUM);
+ if (ret)
+ return ret;
+ }
+
+ val = readl(trng->base + STARFIVE_RAND0 +
+ (i * STARFIVE_RAND_LEN));
+ step = min_t(size_t, len, STARFIVE_RAND_LEN);
+ memcpy(buffer, &val, step);
+ buffer += step;
+ len -= step;
+ }
+
+ return 0;
+}
+
+static int starfive_trng_init(struct starfive_trng_plat *trng)
+{
+ u32 mode, intr = 0;
+
+ /* setup Auto Request/Age register */
+ writel(0, trng->base + STARFIVE_AUTO_AGE);
+ writel(0, trng->base + STARFIVE_AUTO_RQSTS);
+
+ /* clear register: ISTAT */
+ starfive_trng_irq_mask_clear(trng);
+
+ intr |= STARFIVE_IE_ALL;
+ writel(intr, trng->base + STARFIVE_IE);
+
+ mode = readl(trng->base + STARFIVE_MODE);
+
+ switch (trng->mode) {
+ case PRNG_128BIT:
+ mode &= ~STARFIVE_MODE_R256;
+ break;
+ case PRNG_256BIT:
+ mode |= STARFIVE_MODE_R256;
+ break;
+ default:
+ mode |= STARFIVE_MODE_R256;
+ break;
+ }
+
+ writel(mode, trng->base + STARFIVE_MODE);
+
+ return starfive_trng_cmd(trng, STARFIVE_CTRL_EXEC_RANDRESEED);
+}
+
+static int starfive_trng_probe(struct udevice *dev)
+{
+ struct starfive_trng_plat *pdata = dev_get_plat(dev);
+ int err;
+
+ err = clk_enable(pdata->hclk);
+ if (err)
+ return err;
+
+ err = clk_enable(pdata->ahb);
+ if (err)
+ goto err_ahb;
+
+ err = reset_deassert(pdata->rst);
+ if (err)
+ goto err_reset;
+
+ pdata->mode = PRNG_256BIT;
+
+ err = starfive_trng_init(pdata);
+ if (err)
+ goto err_trng_init;
+
+ return 0;
+
+err_trng_init:
+ reset_assert(pdata->rst);
+err_reset:
+ clk_disable(pdata->ahb);
+err_ahb:
+ clk_disable(pdata->hclk);
+
+ return err;
+}
+
+static int starfive_trng_of_to_plat(struct udevice *dev)
+{
+ struct starfive_trng_plat *pdata = dev_get_plat(dev);
+
+ pdata->base = (void *)dev_read_addr(dev);
+ if (!pdata->base)
+ return -ENODEV;
+
+ pdata->hclk = devm_clk_get(dev, "hclk");
+ if (IS_ERR(pdata->hclk))
+ return -ENODEV;
+
+ pdata->ahb = devm_clk_get(dev, "ahb");
+ if (IS_ERR(pdata->ahb))
+ return -ENODEV;
+
+ pdata->rst = devm_reset_control_get(dev, NULL);
+ if (IS_ERR(pdata->rst))
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct dm_rng_ops starfive_trng_ops = {
+ .read = starfive_trng_read,
+};
+
+static const struct udevice_id starfive_trng_match[] = {
+ {
+ .compatible = "starfive,jh7110-trng",
+ },
+ {},
+};
+
+U_BOOT_DRIVER(starfive_trng) = {
+ .name = "jh7110-trng",
+ .id = UCLASS_RNG,
+ .of_match = starfive_trng_match,
+ .probe = starfive_trng_probe,
+ .ops = &starfive_trng_ops,
+ .plat_auto = sizeof(struct starfive_trng_plat),
+ .of_to_plat = starfive_trng_of_to_plat,
+};
diff --git a/drivers/rng/riscv_zkr_rng.c b/drivers/rng/riscv_zkr_rng.c
new file mode 100644
index 0000000..8c9e111
--- /dev/null
+++ b/drivers/rng/riscv_zkr_rng.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * The RISC-V Zkr extension provides CSR seed which provides access to a
+ * random number generator.
+ */
+
+#define LOG_CATEGORY UCLASS_RNG
+
+#include <dm.h>
+#include <interrupt.h>
+#include <log.h>
+#include <rng.h>
+
+#define DRIVER_NAME "riscv_zkr"
+
+enum opst {
+ /** @BIST: built in self test running */
+ BIST = 0b00,
+ /** @WAIT: sufficient amount of entropy is not yet available */
+ WAIT = 0b01,
+ /** @ES16: 16bits of entropy available */
+ ES16 = 0b10,
+ /** @DEAD: unrecoverable self-test error */
+ DEAD = 0b11,
+};
+
+static unsigned long read_seed(void)
+{
+ unsigned long ret;
+
+ __asm__ __volatile__("csrrw %0, seed, x0" : "=r" (ret) : : "memory");
+
+ return ret;
+}
+
+static int riscv_zkr_read(struct udevice *dev, void *data, size_t len)
+{
+ u8 *ptr = data;
+
+ while (len) {
+ u32 val;
+
+ val = read_seed();
+
+ switch (val >> 30) {
+ case BIST:
+ continue;
+ case WAIT:
+ continue;
+ case ES16:
+ *ptr++ = val & 0xff;
+ if (--len) {
+ *ptr++ = val >> 8;
+ --len;
+ }
+ break;
+ case DEAD:
+ return -ENODEV;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * riscv_zkr_probe() - check if the seed register is available
+ *
+ * If the SBI software has not set mseccfg.sseed=1 or the Zkr
+ * extension is not available this probe function will result
+ * in an exception. Currently we cannot recover from this.
+ *
+ * @dev: RNG device
+ * Return: 0 if successfully probed
+ */
+static int riscv_zkr_probe(struct udevice *dev)
+{
+ struct resume_data resume;
+ int ret;
+ u32 val;
+
+ /* Check if reading seed leads to interrupt */
+ set_resume(&resume);
+ ret = setjmp(resume.jump);
+ if (ret)
+ log_debug("Exception %ld reading seed CSR\n", resume.code);
+ else
+ val = read_seed();
+ set_resume(NULL);
+ if (ret)
+ return -ENODEV;
+
+ do {
+ val = read_seed();
+ val >>= 30;
+ } while (val == BIST || val == WAIT);
+
+ if (val == DEAD)
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct dm_rng_ops riscv_zkr_ops = {
+ .read = riscv_zkr_read,
+};
+
+U_BOOT_DRIVER(riscv_zkr) = {
+ .name = DRIVER_NAME,
+ .id = UCLASS_RNG,
+ .ops = &riscv_zkr_ops,
+ .probe = riscv_zkr_probe,
+};
+
+U_BOOT_DRVINFO(cpu_riscv_zkr) = {
+ .name = DRIVER_NAME,
+};
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index c034ab5..e4cc4ee 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -6,7 +6,6 @@
* Copyright (C) 2002 - 2008 Paul Mundt
*/
-#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/processor.h>
diff --git a/include/cbfs.h b/include/cbfs.h
index 38efb1d..2bc5de2 100644
--- a/include/cbfs.h
+++ b/include/cbfs.h
@@ -22,7 +22,7 @@
enum cbfs_filetype {
CBFS_TYPE_BOOTBLOCK = 0x01,
CBFS_TYPE_CBFSHEADER = 0x02,
- CBFS_TYPE_STAGE = 0x10,
+ CBFS_TYPE_LEGACY_STAGE = 0x10,
CBFS_TYPE_PAYLOAD = 0x20,
CBFS_TYPE_SELF = CBFS_TYPE_PAYLOAD,
diff --git a/include/clk.h b/include/clk.h
index d912852..249c0e0 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -223,9 +223,11 @@
static inline struct clk *devm_clk_get_optional(struct udevice *dev,
const char *id)
{
+ int ret;
struct clk *clk = devm_clk_get(dev, id);
- if (PTR_ERR(clk) == -ENODATA)
+ ret = PTR_ERR(clk);
+ if (ret == -ENODATA || ret == -ENOENT)
return NULL;
return clk;
@@ -243,7 +245,7 @@
*
* Return: zero on success, or -ve error code.
*/
-int clk_release_all(struct clk *clk, int count);
+int clk_release_all(struct clk *clk, unsigned int count);
/**
* devm_clk_put - "free" a managed clock source
@@ -307,7 +309,7 @@
return -ENOSYS;
}
-static inline int clk_release_all(struct clk *clk, int count)
+static inline int clk_release_all(struct clk *clk, unsigned int count)
{
return -ENOSYS;
}
@@ -335,7 +337,7 @@
int ret;
ret = clk_get_by_name(dev, name, clk);
- if (ret == -ENODATA)
+ if (ret == -ENODATA || ret == -ENOENT)
return 0;
return ret;
@@ -359,7 +361,7 @@
int ret;
ret = clk_get_by_name_nodev(node, name, clk);
- if (ret == -ENODATA)
+ if (ret == -ENODATA || ret == -ENOENT)
return 0;
return ret;
diff --git a/include/configs/arbel.h b/include/configs/arbel.h
index 891257b..576ee37 100644
--- a/include/configs/arbel.h
+++ b/include/configs/arbel.h
@@ -7,11 +7,15 @@
#define __CONFIG_ARBEL_H
#define CFG_SYS_SDRAM_BASE 0x0
-#define CFG_SYS_BOOTMAPSZ (30 << 20)
+#define CFG_SYS_BOOTMAPSZ (128 << 20)
#define CFG_SYS_BOOTM_LEN (20 << 20)
#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
#define CFG_SYS_INIT_RAM_SIZE 0x8000
+#define CFG_SYS_BAUDRATE_TABLE \
+ { 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 }
+
+
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \
"stdin=serial\0" \
diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
index 3347c11..3ada21c 100644
--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2022 ARM Limited
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
* (C) Copyright 2022 Linaro
* Rui Miguel Silva <rui.silva@linaro.org>
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
@@ -29,5 +29,6 @@
#include <config_distro_bootcmd.h>
+#define CFG_EXTRA_ENV_SETTINGS BOOTENV
#endif
diff --git a/include/configs/poleg.h b/include/configs/poleg.h
index 1e96e83..2a2d85c 100644
--- a/include/configs/poleg.h
+++ b/include/configs/poleg.h
@@ -13,6 +13,8 @@
#define CFG_SYS_BOOTMAPSZ (0x30 << 20)
#define CFG_SYS_SDRAM_BASE 0x0
+#define CFG_SYS_BAUDRATE_TABLE { 57600, 115200, 230400, 460800 }
+
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
"stdin=serial\0" \
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 74150b7..de8bfc1 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -36,7 +36,7 @@
"name=system,size=-,bootable,type=${type_guid_gpt_system};"
#define CFG_EXTRA_ENV_SETTINGS \
- "kernel_addr_r=0x84000000\0" \
+ "kernel_addr_r=0x80200000\0" \
"kernel_comp_addr_r=0x88000000\0" \
"kernel_comp_size=0x4000000\0" \
"fdt_addr_r=0x8c000000\0" \
diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h
index cd7359c..e36e63e 100644
--- a/include/configs/synquacer.h
+++ b/include/configs/synquacer.h
@@ -41,20 +41,6 @@
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
-#define DEFAULT_DFU_ALT_INFO
-#else
-#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
- "mtd nor1=u-boot.bin raw 200000 100000;" \
- "fip.bin raw 180000 78000;" \
- "optee.bin raw 500000 100000\0"
-#endif
-
-/* GUIDs for capsule updatable firmware images */
-#define DEVELOPERBOX_UBOOT_IMAGE_GUID \
- EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \
- 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00)
-
-#ifdef CONFIG_FWU_MULTI_BANK_UPDATE
#define DEVELOPERBOX_FIP_IMAGE_GUID \
EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \
0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08)
@@ -64,10 +50,6 @@
0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98)
#endif
-#define DEVELOPERBOX_OPTEE_IMAGE_GUID \
- EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \
- 0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30)
-
/* Distro boot settings */
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
@@ -107,7 +89,6 @@
"ramdisk_addr_r=0xa0000000\0" \
"scriptaddr=0x88000000\0" \
"pxefile_addr_r=0x88100000\0" \
- DEFAULT_DFU_ALT_INFO \
BOOTENV
#endif /* __CONFIG_H */
diff --git a/include/i2c.h b/include/i2c.h
index ef3820e..4e59009 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -538,6 +538,18 @@
struct udevice **devp);
/**
+ * i2c_get_chip_by_phandle() - get a device to use to access a chip
+ * based on a phandle property pointing to it
+ *
+ * @parent: Parent device containing the phandle pointer
+ * @name: Name of phandle property in the parent device node
+ * @devp: Returns pointer to new device or NULL if not found
+ * Return: 0 on success, -ve on failure
+ */
+int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name,
+ struct udevice **devp);
+
+/**
* i2c_chip_of_to_plat() - Decode standard I2C platform data
*
* This decodes the chip address from a device tree node and puts it into
diff --git a/include/interrupt.h b/include/interrupt.h
new file mode 100644
index 0000000..46ef2e1
--- /dev/null
+++ b/include/interrupt.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <asm/setjmp.h>
+
+/**
+ * struct resume_data - data for resume after interrupt
+ */
+struct resume_data {
+ /** @jump: longjmp buffer */
+ jmp_buf jump;
+ /** @code: exception code */
+ ulong code;
+};
+
+/**
+ * set_resume() - set longjmp buffer for resuming after exception
+ *
+ * By calling this function it is possible to use a long jump to catch an
+ * exception. The caller sets the long jump buffer with set_resume() and then
+ * executes setjmp(). If an exception occurs, the code will return to the
+ * setjmp caller(). The exception code will be returned in @data->code.
+ *
+ * After the critical operation call set_resume(NULL) so that an exception in
+ * another part of the code will not accidently invoke the long jump.
+ *
+ * .. code-block:: c
+ *
+ * // This example shows how to use set_resume().
+ *
+ * struct resume_data resume;
+ * int ret;
+ *
+ * set_resume(&resume);
+ * ret = setjmp(resume.jump);
+ * if (ret) {
+ * printf("An exception %ld occurred\n", resume.code);
+ * } else {
+ * // Do what might raise an exception here.
+ * }
+ * set_resume(NULL);
+ *
+ * @data: pointer to structure with longjmp address
+ * Return: 0 before an exception, 1 after an exception occurred
+ */
+void set_resume(struct resume_data *data);
diff --git a/include/sdhci.h b/include/sdhci.h
index 70fefca..a1b74e3 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -57,6 +57,7 @@
#define SDHCI_PRESENT_STATE 0x24
#define SDHCI_CMD_INHIBIT BIT(0)
#define SDHCI_DATA_INHIBIT BIT(1)
+#define SDHCI_DAT_ACTIVE BIT(2)
#define SDHCI_DOING_WRITE BIT(8)
#define SDHCI_DOING_READ BIT(9)
#define SDHCI_SPACE_AVAILABLE BIT(10)
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index f5b2059..f640db8 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -973,6 +973,26 @@
}
BOOTSTD_TEST(bootflow_cmdline, 0);
+/* test a few special changes to a long command line */
+static int bootflow_cmdline_special(struct unit_test_state *uts)
+{
+ char buf[500];
+ int pos;
+
+ /*
+ * check handling of an argument which has an embedded '=', as well as
+ * handling of a argument which partially matches ("ro" and "root")
+ */
+ ut_asserteq(32, cmdline_set_arg(
+ buf, sizeof(buf),
+ "loglevel=7 root=PARTUUID=d68352e3 rootwait ro noinitrd",
+ "root", NULL, &pos));
+ ut_asserteq_str("loglevel=7 rootwait ro noinitrd", buf);
+
+ return 0;
+}
+BOOTSTD_TEST(bootflow_cmdline_special, 0);
+
/* Test ChromiumOS bootmeth */
static int bootflow_cros(struct unit_test_state *uts)
{
diff --git a/tools/binman/btool/openssl.py b/tools/binman/btool/openssl.py
index aad3b61..7ee2683 100644
--- a/tools/binman/btool/openssl.py
+++ b/tools/binman/btool/openssl.py
@@ -155,6 +155,7 @@
C, ST, L, O, OU, CN and emailAddress
cert_type (int): Certification type
bootcore (int): Booting core
+ bootcore_opts(int): Booting core option, lockstep (0) or split (2) mode
load_addr (int): Load address of image
sha (int): Hash function
@@ -225,7 +226,7 @@
imagesize_sbl, hashval_sbl, load_addr_sysfw, imagesize_sysfw,
hashval_sysfw, load_addr_sysfw_data, imagesize_sysfw_data,
hashval_sysfw_data, sysfw_inner_cert_ext_boot_block,
- dm_data_ext_boot_block):
+ dm_data_ext_boot_block, bootcore_opts):
"""Create a certificate
Args:
@@ -241,6 +242,7 @@
bootcore (int): Booting core
load_addr (int): Load address of image
sha (int): Hash function
+ bootcore_opts (int): Booting core option, lockstep (0) or split (2) mode
Returns:
str: Tool output
@@ -285,7 +287,7 @@
[sbl]
compType = INTEGER:1
bootCore = INTEGER:16
-compOpts = INTEGER:0
+compOpts = INTEGER:{bootcore_opts}
destAddr = FORMAT:HEX,OCT:{load_addr:08x}
compSize = INTEGER:{imagesize_sbl}
shaType = OID:{sha_type}
diff --git a/tools/binman/cbfs_util.py b/tools/binman/cbfs_util.py
index fc56b40..671cafa 100644
--- a/tools/binman/cbfs_util.py
+++ b/tools/binman/cbfs_util.py
@@ -42,27 +42,24 @@
FILE_HEADER_FORMAT = b'>8sIIII'
FILE_HEADER_LEN = 0x18
FILE_MAGIC = b'LARCHIVE'
-FILENAME_ALIGN = 16 # Filename lengths are aligned to this
+ATTRIBUTE_ALIGN = 4 # All attribute sizes must be divisible by this
-# A stage header containing information about 'stage' files
+# A stage-header attribute containing information about 'stage' files
# Yes this is correct: this header is in litte-endian format
-STAGE_FORMAT = '<IQQII'
-STAGE_LEN = 0x1c
+ATTR_STAGE_FORMAT = '>IIQII'
+ATTR_STAGE_LEN = 0x18
# An attribute describring the compression used in a file
ATTR_COMPRESSION_FORMAT = '>IIII'
ATTR_COMPRESSION_LEN = 0x10
# Attribute tags
-# Depending on how the header was initialised, it may be backed with 0x00 or
-# 0xff. Support both.
-FILE_ATTR_TAG_UNUSED = 0
-FILE_ATTR_TAG_UNUSED2 = 0xffffffff
FILE_ATTR_TAG_COMPRESSION = 0x42435a4c
FILE_ATTR_TAG_HASH = 0x68736148
FILE_ATTR_TAG_POSITION = 0x42435350 # PSCB
FILE_ATTR_TAG_ALIGNMENT = 0x42434c41 # ALCB
FILE_ATTR_TAG_PADDING = 0x47444150 # PDNG
+FILE_ATTR_TAG_STAGEHEADER = 0x53746748 # StgH
# This is 'the size of bootblock reserved in firmware image (cbfs.txt)'
# Not much more info is available, but we set it to 4, due to this comment in
@@ -100,7 +97,8 @@
# File types. Only supported ones are included here
TYPE_CBFSHEADER = 0x02 # Master header, HEADER_FORMAT
-TYPE_STAGE = 0x10 # Stage, holding an executable, see STAGE_FORMAT
+TYPE_LEGACY_STAGE = 0x10 # Stage, holding an executable
+TYPE_STAGE = 0x11 # New-type stage with ATTR_STAGE_FORMAT
TYPE_RAW = 0x50 # Raw file, possibly compressed
TYPE_EMPTY = 0xffffffff # Empty data
@@ -190,7 +188,7 @@
String with required padding (at least one 0x00 byte) at the end
"""
val = tools.to_bytes(instr)
- pad_len = align_int(len(val) + 1, FILENAME_ALIGN)
+ pad_len = align_int(len(val) + 1, ATTRIBUTE_ALIGN)
return val + tools.get_bytes(0, pad_len - len(val))
@@ -304,7 +302,7 @@
CbfsFile object containing the file information
"""
cfile = CbfsFile('', TYPE_EMPTY, b'', None)
- cfile.size = space_to_use - FILE_HEADER_LEN - FILENAME_ALIGN
+ cfile.size = space_to_use - FILE_HEADER_LEN - ATTRIBUTE_ALIGN
cfile.erase_byte = erase_byte
return cfile
@@ -331,9 +329,10 @@
name = _pack_string(self.name)
hdr_len = len(name) + FILE_HEADER_LEN
if self.ftype == TYPE_STAGE:
- pass
+ hdr_len += ATTR_STAGE_LEN
elif self.ftype == TYPE_RAW:
- hdr_len += ATTR_COMPRESSION_LEN
+ if self.compress:
+ hdr_len += ATTR_COMPRESSION_LEN
elif self.ftype == TYPE_EMPTY:
pass
else:
@@ -359,9 +358,9 @@
data = self.data
if self.ftype == TYPE_STAGE:
elf_data = elf.DecodeElf(data, self.base_address)
- content = struct.pack(STAGE_FORMAT, self.compress,
- elf_data.entry, elf_data.load,
- len(elf_data.data), elf_data.memsize)
+ attr = struct.pack(ATTR_STAGE_FORMAT, FILE_ATTR_TAG_STAGEHEADER,
+ ATTR_STAGE_LEN, elf_data.load,
+ elf_data.entry - elf_data.load, elf_data.memsize)
data = elf_data.data
elif self.ftype == TYPE_RAW:
orig_data = data
@@ -369,9 +368,11 @@
data = self.comp_bintool.compress(orig_data)
self.memlen = len(orig_data)
self.data_len = len(data)
- attr = struct.pack(ATTR_COMPRESSION_FORMAT,
- FILE_ATTR_TAG_COMPRESSION, ATTR_COMPRESSION_LEN,
- self.compress, self.memlen)
+ if self.compress:
+ attr = struct.pack(ATTR_COMPRESSION_FORMAT,
+ FILE_ATTR_TAG_COMPRESSION,
+ ATTR_COMPRESSION_LEN, self.compress,
+ self.memlen)
elif self.ftype == TYPE_EMPTY:
data = tools.get_bytes(self.erase_byte, self.size)
else:
@@ -391,6 +392,8 @@
raise ValueError("Internal error: CBFS file '%s': Requested offset %#x but current output position is %#x" %
(self.name, self.cbfs_offset, offset))
pad = tools.get_bytes(pad_byte, pad_len)
+ if attr_pos:
+ attr_pos += pad_len
hdr_len += pad_len
# This is the offset of the start of the file's data,
@@ -405,9 +408,9 @@
if expected_len != actual_len: # pragma: no cover
# Test coverage of this is not available since this should never
# happen. It probably indicates that get_header_len() is broken.
- raise ValueError("Internal error: CBFS file '%s': Expected headers of %#x bytes, got %#d" %
+ raise ValueError("Internal error: CBFS file '%s': Expected headers of %#x bytes, got %#x" %
(self.name, expected_len, actual_len))
- return hdr + name + attr + pad + content + data, hdr_len
+ return hdr + name + pad + attr + content + data, hdr_len
class CbfsWriter(object):
@@ -453,6 +456,9 @@
self._arch = arch
self._bootblock_size = 0
self._erase_byte = 0xff
+
+ # Small padding to align a file uses 0
+ self._small_pad_byte = 0
self._align = ENTRY_ALIGN
self._add_fileheader = False
if self._arch == ARCHITECTURE_X86:
@@ -474,7 +480,7 @@
self._bootblock_size, self._align)
self._hdr_at_start = True
- def _skip_to(self, fd, offset):
+ def _skip_to(self, fd, offset, pad_byte):
"""Write out pad bytes until a given offset
Args:
@@ -484,16 +490,16 @@
if fd.tell() > offset:
raise ValueError('No space for data before offset %#x (current offset %#x)' %
(offset, fd.tell()))
- fd.write(tools.get_bytes(self._erase_byte, offset - fd.tell()))
+ fd.write(tools.get_bytes(pad_byte, offset - fd.tell()))
- def _pad_to(self, fd, offset):
+ def _pad_to(self, fd, offset, pad_byte):
"""Write out pad bytes and/or an empty file until a given offset
Args:
fd: File objext to write to
offset: Offset to write to
"""
- self._align_to(fd, self._align)
+ self._align_to(fd, self._align, pad_byte)
upto = fd.tell()
if upto > offset:
raise ValueError('No space for data before pad offset %#x (current offset %#x)' %
@@ -502,9 +508,9 @@
if todo:
cbf = CbfsFile.empty(todo, self._erase_byte)
fd.write(cbf.get_data_and_offset()[0])
- self._skip_to(fd, offset)
+ self._skip_to(fd, offset, pad_byte)
- def _align_to(self, fd, align):
+ def _align_to(self, fd, align, pad_byte):
"""Write out pad bytes until a given alignment is reached
This only aligns if the resulting output would not reach the end of the
@@ -518,7 +524,7 @@
"""
offset = align_int(fd.tell(), align)
if offset < self._size:
- self._skip_to(fd, offset)
+ self._skip_to(fd, offset, pad_byte)
def add_file_stage(self, name, data, cbfs_offset=None):
"""Add a new stage file to the CBFS
@@ -568,7 +574,7 @@
raise ValueError('No space for header at offset %#x (current offset %#x)' %
(self._header_offset, fd.tell()))
if not add_fileheader:
- self._pad_to(fd, self._header_offset)
+ self._pad_to(fd, self._header_offset, self._erase_byte)
hdr = struct.pack(HEADER_FORMAT, HEADER_MAGIC, HEADER_VERSION2,
self._size, self._bootblock_size, self._align,
self._contents_offset, self._arch, 0xffffffff)
@@ -580,7 +586,7 @@
fd.write(name)
self._header_offset = fd.tell()
fd.write(hdr)
- self._align_to(fd, self._align)
+ self._align_to(fd, self._align, self._erase_byte)
else:
fd.write(hdr)
@@ -597,24 +603,26 @@
# THe header can go at the start in some cases
if self._hdr_at_start:
self._write_header(fd, add_fileheader=self._add_fileheader)
- self._skip_to(fd, self._contents_offset)
+ self._skip_to(fd, self._contents_offset, self._erase_byte)
# Write out each file
for cbf in self._files.values():
# Place the file at its requested place, if any
offset = cbf.calc_start_offset()
if offset is not None:
- self._pad_to(fd, align_int_down(offset, self._align))
+ self._pad_to(fd, align_int_down(offset, self._align),
+ self._erase_byte)
pos = fd.tell()
- data, data_offset = cbf.get_data_and_offset(pos, self._erase_byte)
+ data, data_offset = cbf.get_data_and_offset(pos,
+ self._small_pad_byte)
fd.write(data)
- self._align_to(fd, self._align)
+ self._align_to(fd, self._align, self._erase_byte)
cbf.calced_cbfs_offset = pos + data_offset
if not self._hdr_at_start:
self._write_header(fd, add_fileheader=self._add_fileheader)
# Pad to the end and write a pointer to the CBFS master header
- self._pad_to(fd, self._base_address or self._size - 4)
+ self._pad_to(fd, self._base_address or self._size - 4, self._erase_byte)
rel_offset = self._header_offset - self._size
fd.write(struct.pack('<I', rel_offset & 0xffffffff))
@@ -734,26 +742,28 @@
print('name', name)
# If there are attribute headers present, read those
- compress = self._read_attr(fd, file_pos, attr, offset)
- if compress is None:
+ attrs = self._read_attr(fd, file_pos, attr, offset)
+ if attrs is None:
return False
# Create the correct CbfsFile object depending on the type
cfile = None
cbfs_offset = file_pos + offset
fd.seek(cbfs_offset, io.SEEK_SET)
+ if DEBUG:
+ print(f'ftype {ftype:x}')
if ftype == TYPE_CBFSHEADER:
self._read_header(fd)
elif ftype == TYPE_STAGE:
- data = fd.read(STAGE_LEN)
cfile = CbfsFile.stage(self.stage_base_address, name, b'',
cbfs_offset)
- (cfile.compress, cfile.entry, cfile.load, cfile.data_len,
- cfile.memlen) = struct.unpack(STAGE_FORMAT, data)
- cfile.data = fd.read(cfile.data_len)
+ cfile.load, entry_offset, cfile.memlen = attrs
+ cfile.entry = cfile.load + entry_offset
+ cfile.data = fd.read(cfile.memlen)
+ cfile.data_len = cfile.memlen
elif ftype == TYPE_RAW:
data = fd.read(size)
- cfile = CbfsFile.raw(name, data, cbfs_offset, compress)
+ cfile = CbfsFile.raw(name, data, cbfs_offset, attrs)
cfile.decompress()
if DEBUG:
print('data', data)
@@ -777,8 +787,8 @@
"""Read attributes from the file
CBFS files can have attributes which are things that cannot fit into the
- header. The only attributes currently supported are compression and the
- unused tag.
+ header. The only attributes currently supported are compression, stage
+ header and the unused tag
Args:
fd: File to read from
@@ -788,11 +798,16 @@
attributes)
Returns:
- Compression to use for the file (COMPRESS_...)
+ Either:
+ Compression to use for the file (COMPRESS_...)
+ tuple containing stage info:
+ load address
+ entry offset
+ memory size
"""
- compress = COMPRESS_NONE
+ attrs = None
if not attr:
- return compress
+ return COMPRESS_NONE
attr_size = offset - attr
fd.seek(file_pos + attr, io.SEEK_SET)
while attr_size:
@@ -807,12 +822,15 @@
# We don't currently use this information
atag, alen, compress, _decomp_size = struct.unpack(
ATTR_COMPRESSION_FORMAT, data)
- elif atag == FILE_ATTR_TAG_UNUSED2:
- break
+ attrs = compress
+ elif atag == FILE_ATTR_TAG_STAGEHEADER:
+ atag, alen, load, entry_offset, memsize = struct.unpack(
+ ATTR_STAGE_FORMAT, data)
+ attrs = (load, entry_offset, memsize)
else:
print('Unknown attribute tag %x' % atag)
attr_size -= len(data)
- return compress
+ return attrs
def _read_header(self, fd):
"""Read the master header
@@ -843,7 +861,8 @@
def _read_string(cls, fd):
"""Read a string from a file
- This reads a string and aligns the data to the next alignment boundary
+ This reads a string and aligns the data to the next alignment boundary.
+ The string must be nul-terminated
Args:
fd: File to read from
@@ -854,8 +873,8 @@
"""
val = b''
while True:
- data = fd.read(FILENAME_ALIGN)
- if len(data) < FILENAME_ALIGN:
+ data = fd.read(ATTRIBUTE_ALIGN)
+ if len(data) < ATTRIBUTE_ALIGN:
return None
pos = data.find(b'\0')
if pos == -1:
diff --git a/tools/binman/cbfs_util_test.py b/tools/binman/cbfs_util_test.py
index ee951d1..4c415b7 100755
--- a/tools/binman/cbfs_util_test.py
+++ b/tools/binman/cbfs_util_test.py
@@ -96,7 +96,7 @@
self.assertEqual(arch, cbfs.arch)
return cbfs
- def _check_uboot(self, cbfs, ftype=cbfs_util.TYPE_RAW, offset=0x38,
+ def _check_uboot(self, cbfs, ftype=cbfs_util.TYPE_RAW, offset=0x20,
data=U_BOOT_DATA, cbfs_offset=None):
"""Check that the U-Boot file is as expected
@@ -122,7 +122,7 @@
self.assertEqual(len(data), cfile.memlen)
return cfile
- def _check_dtb(self, cbfs, offset=0x38, data=U_BOOT_DTB_DATA,
+ def _check_dtb(self, cbfs, offset=0x24, data=U_BOOT_DTB_DATA,
cbfs_offset=None):
"""Check that the U-Boot dtb file is as expected
@@ -391,7 +391,7 @@
cbfs_util.DEBUG = True
with test_util.capture_sys_output() as (stdout, _stderr):
cbfs_util.CbfsReader(data)
- self.assertEqual('name u-boot\ndata %s\n' % U_BOOT_DATA,
+ self.assertEqual('name u-boot\nftype 50\ndata %s\n' % U_BOOT_DATA,
stdout.getvalue())
finally:
cbfs_util.DEBUG = False
@@ -437,8 +437,9 @@
pos = fd.tell()
# Create a new CBFS with only the first 4 bytes of the compression tag,
- # then try to read the file
- tag_pos = pos + cbfs_util.FILE_HEADER_LEN + cbfs_util.FILENAME_ALIGN
+ # then try to read the file. Note that the tag gets pushed out 4 bytes
+ tag_pos = (4 + pos + cbfs_util.FILE_HEADER_LEN +
+ cbfs_util.ATTRIBUTE_ALIGN)
newdata = data[:tag_pos + 4]
with test_util.capture_sys_output() as (stdout, _stderr):
with io.BytesIO(newdata) as fd:
@@ -474,7 +475,7 @@
self._compare_expected_cbfs(data, cbfs_fname)
def test_cbfs_stage(self):
- """Tests handling of a Coreboot Filesystem (CBFS)"""
+ """Tests handling of a CBFS stage"""
if not elf.ELF_TOOLS:
self.skipTest('Python elftools not available')
elf_fname = os.path.join(self._indir, 'cbfs-stage.elf')
@@ -489,7 +490,7 @@
load = 0xfef20000
entry = load + 2
- cfile = self._check_uboot(cbfs, cbfs_util.TYPE_STAGE, offset=0x28,
+ cfile = self._check_uboot(cbfs, cbfs_util.TYPE_STAGE, offset=0x38,
data=U_BOOT_DATA + U_BOOT_DTB_DATA)
self.assertEqual(entry, cfile.entry)
@@ -520,7 +521,7 @@
self.assertIn('u-boot', cbfs.files)
cfile = cbfs.files['u-boot']
self.assertEqual(cfile.name, 'u-boot')
- self.assertEqual(cfile.offset, 56)
+ self.assertEqual(cfile.offset, 0x30)
self.assertEqual(cfile.data, COMPRESS_DATA)
self.assertEqual(cfile.ftype, cbfs_util.TYPE_RAW)
self.assertEqual(cfile.compress, cbfs_util.COMPRESS_LZ4)
@@ -529,7 +530,7 @@
self.assertIn('u-boot-dtb', cbfs.files)
cfile = cbfs.files['u-boot-dtb']
self.assertEqual(cfile.name, 'u-boot-dtb')
- self.assertEqual(cfile.offset, 56)
+ self.assertEqual(cfile.offset, 0x34)
self.assertEqual(cfile.data, COMPRESS_DATA)
self.assertEqual(cfile.ftype, cbfs_util.TYPE_RAW)
self.assertEqual(cfile.compress, cbfs_util.COMPRESS_LZMA)
@@ -598,8 +599,8 @@
data = cbw.get_data()
cbfs = cbfs_util.CbfsReader(data)
- self.assertEqual(0x38, cbfs.files['u-boot'].cbfs_offset)
- self.assertEqual(0x78, cbfs.files['u-boot-dtb'].cbfs_offset)
+ self.assertEqual(0x20, cbfs.files['u-boot'].cbfs_offset)
+ self.assertEqual(0x64, cbfs.files['u-boot-dtb'].cbfs_offset)
if __name__ == '__main__':
diff --git a/tools/binman/control.py b/tools/binman/control.py
index c6d3205..2f00279 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -858,6 +858,8 @@
data = state.GetFdtForEtype('u-boot-dtb').GetContents()
elf.UpdateFile(*elf_params, data)
+ bintool.Bintool.set_missing_list(None)
+
# This can only be True if -M is provided, since otherwise binman
# would have raised an error already
if invalid:
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index e7b4e93..2402adb 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1944,6 +1944,7 @@
- core: core on which bootloader runs, valid cores are 'secure' and 'public'
- content: phandle of SPL in case of legacy bootflow or phandles of component binaries
in case of combined bootflow
+ - core-opts (optional): lockstep (0) or split (2) mode set to 0 by default
The following properties are only for generating a combined bootflow binary:
- sysfw-inner-cert: boolean if binary contains sysfw inner certificate
diff --git a/tools/binman/etype/ti_secure_rom.py b/tools/binman/etype/ti_secure_rom.py
index 9a7ac9e..f6fc3f9 100644
--- a/tools/binman/etype/ti_secure_rom.py
+++ b/tools/binman/etype/ti_secure_rom.py
@@ -32,6 +32,7 @@
- core: core on which bootloader runs, valid cores are 'secure' and 'public'
- content: phandle of SPL in case of legacy bootflow or phandles of component binaries
in case of combined bootflow
+ - core-opts (optional): lockstep (0) or split (2) mode set to 0 by default
The following properties are only for generating a combined bootflow binary:
- sysfw-inner-cert: boolean if binary contains sysfw inner certificate
@@ -69,6 +70,7 @@
self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1)
self.sha = fdt_util.GetInt(self._node, 'sha', 512)
self.core = fdt_util.GetString(self._node, 'core', 'secure')
+ self.bootcore_opts = fdt_util.GetInt(self._node, 'core-opts')
self.key_fname = self.GetEntryArgsOrProps([
EntryArg('keyfile', str)], required=True)[0]
if self.combined:
@@ -97,17 +99,19 @@
bytes content of the entry, which is the certificate binary for the
provided data
"""
+ if self.bootcore_opts is None:
+ self.bootcore_opts = 0
+
if self.core == 'secure':
if self.countersign:
self.cert_type = 3
else:
self.cert_type = 2
self.bootcore = 0
- self.bootcore_opts = 32
else:
self.cert_type = 1
self.bootcore = 16
- self.bootcore_opts = 0
+
return super().GetCertificate(required=required, type='rom')
def CombinedGetCertificate(self, required):
@@ -126,6 +130,9 @@
self.num_comps = 3
self.sha_type = SHA_OIDS[self.sha]
+ if self.bootcore_opts is None:
+ self.bootcore_opts = 0
+
# sbl
self.content = fdt_util.GetPhandleList(self._node, 'content-sbl')
input_data_sbl = self.GetContents(required)
diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py
index d028cfe..fc0bb12 100644
--- a/tools/binman/etype/x509_cert.py
+++ b/tools/binman/etype/x509_cert.py
@@ -136,7 +136,8 @@
imagesize_sysfw_data=self.imagesize_sysfw_data,
hashval_sysfw_data=self.hashval_sysfw_data,
sysfw_inner_cert_ext_boot_block=self.sysfw_inner_cert_ext_boot_block,
- dm_data_ext_boot_block=self.dm_data_ext_boot_block
+ dm_data_ext_boot_block=self.dm_data_ext_boot_block,
+ bootcore_opts=self.bootcore_opts
)
if stdout is not None:
data = tools.read_file(output_fname)
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 16156b7..5ace2a8 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -2667,12 +2667,12 @@
'cbfs:offset': 0,
'cbfs:size': len(data),
'cbfs:image-pos': 0,
- 'cbfs/u-boot:offset': 0x38,
+ 'cbfs/u-boot:offset': 0x30,
'cbfs/u-boot:uncomp-size': len(U_BOOT_DATA),
- 'cbfs/u-boot:image-pos': 0x38,
- 'cbfs/u-boot-dtb:offset': 0xb8,
+ 'cbfs/u-boot:image-pos': 0x30,
+ 'cbfs/u-boot-dtb:offset': 0xa4,
'cbfs/u-boot-dtb:size': len(U_BOOT_DATA),
- 'cbfs/u-boot-dtb:image-pos': 0xb8,
+ 'cbfs/u-boot-dtb:image-pos': 0xa4,
}, props)
def testCbfsBadType(self):
@@ -2854,7 +2854,7 @@
' u-boot 0 4 u-boot 0',
' section 100 %x section 100' % section_size,
' cbfs 100 400 cbfs 0',
-' u-boot 138 4 u-boot 38',
+' u-boot 120 4 u-boot 20',
' u-boot-dtb 180 105 u-boot-dtb 80 3c9',
' u-boot-dtb 500 %x u-boot-dtb 400 3c9' % fdt_size,
' fdtmap %x 3bd fdtmap %x' %
diff --git a/tools/binman/test/297_ti_secure_rom.dts b/tools/binman/test/297_ti_secure_rom.dts
index d131376..1a3eca9 100644
--- a/tools/binman/test/297_ti_secure_rom.dts
+++ b/tools/binman/test/297_ti_secure_rom.dts
@@ -9,6 +9,7 @@
binman {
ti-secure-rom {
content = <&unsecure_binary>;
+ core-opts = <2>;
};
unsecure_binary: blob-ext {
filename = "ti_unsecure.bin";
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 5305477..3e42c98 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -35,6 +35,10 @@
# which indicates that BREAK_ME has an empty default
RE_NO_DEFAULT = re.compile(b'\((\w+)\) \[] \(NEW\)')
+# Symbol types which appear in the bloat feature (-B). Others are silently
+# dropped when reading in the 'nm' output
+NM_SYMBOL_TYPES = 'tTdDbBr'
+
"""
Theory of Operation
@@ -693,7 +697,7 @@
parts = line.split()
if line and len(parts) == 3:
size, type, name = line.split()
- if type in 'tTdDbB':
+ if type in NM_SYMBOL_TYPES:
# function names begin with '.' on 64-bit powerpc
if '.' in name[1:]:
name = 'static.' + name.split('.')[0]
diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py
index 8eba5d3..197ac1a 100755
--- a/tools/patman/__main__.py
+++ b/tools/patman/__main__.py
@@ -103,6 +103,8 @@
default=True, help="Don't add Signed-off-by to patches")
send.add_argument('--smtp-server', type=str,
help="Specify the SMTP server to 'git send-email'")
+send.add_argument('--keep-change-id', action='store_true',
+ help='Preserve Change-Id tags in patches to send.')
send.add_argument('patchfiles', nargs='*')
diff --git a/tools/patman/control.py b/tools/patman/control.py
index 916ddf8..b292da9 100644
--- a/tools/patman/control.py
+++ b/tools/patman/control.py
@@ -16,11 +16,14 @@
from patman import patchstream
from u_boot_pylib import terminal
+
def setup():
"""Do required setup before doing anything"""
gitutil.setup()
-def prepare_patches(col, branch, count, start, end, ignore_binary, signoff):
+
+def prepare_patches(col, branch, count, start, end, ignore_binary, signoff,
+ keep_change_id=False):
"""Figure out what patches to generate, then generate them
The patch files are written to the current directory, e.g. 0001_xxx.patch
@@ -35,6 +38,7 @@
end (int): End patch to use (0=last one in series, 1=one before that,
etc.)
ignore_binary (bool): Don't generate patches for binary files
+ keep_change_id (bool): Preserve the Change-Id tag.
Returns:
Tuple:
@@ -59,11 +63,12 @@
branch, start, to_do, ignore_binary, series, signoff)
# Fix up the patch files to our liking, and insert the cover letter
- patchstream.fix_patches(series, patch_files)
+ patchstream.fix_patches(series, patch_files, keep_change_id)
if cover_fname and series.get('cover'):
patchstream.insert_cover_letter(cover_fname, series, to_do)
return series, cover_fname, patch_files
+
def check_patches(series, patch_files, run_checkpatch, verbose, use_tree):
"""Run some checks on a set of patches
@@ -166,7 +171,8 @@
col = terminal.Color()
series, cover_fname, patch_files = prepare_patches(
col, args.branch, args.count, args.start, args.end,
- args.ignore_binary, args.add_signoff)
+ args.ignore_binary, args.add_signoff,
+ keep_change_id=args.keep_change_id)
ok = check_patches(series, patch_files, args.check_patch,
args.verbose, args.check_patch_use_tree)
diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py
index b0a12f2..10ea5ff 100644
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
@@ -147,8 +147,9 @@
if remote == '.':
return merge, None
elif remote and merge:
- leaf = merge.split('/')[-1]
- return '%s/%s' % (remote, leaf), None
+ # Drop the initial refs/heads from merge
+ leaf = merge.split('/', maxsplit=2)[2:]
+ return '%s/%s' % (remote, '/'.join(leaf)), None
else:
raise ValueError("Cannot determine upstream branch for branch "
"'%s' remote='%s', merge='%s'"
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index f91669a..e2e2a83 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -68,6 +68,7 @@
STATE_PATCH_HEADER = 2 # In patch header (after the subject)
STATE_DIFFS = 3 # In the diff part (past --- line)
+
class PatchStream:
"""Class for detecting/injecting tags in a patch or series of patches
@@ -76,7 +77,7 @@
unwanted tags or inject additional ones. These correspond to the two
phases of processing.
"""
- def __init__(self, series, is_log=False):
+ def __init__(self, series, is_log=False, keep_change_id=False):
self.skip_blank = False # True to skip a single blank line
self.found_test = False # Found a TEST= line
self.lines_after_test = 0 # Number of lines found after TEST=
@@ -86,6 +87,7 @@
self.section = [] # The current section...END section
self.series = series # Info about the patch series
self.is_log = is_log # True if indent like git log
+ self.keep_change_id = keep_change_id # True to keep Change-Id tags
self.in_change = None # Name of the change list we are in
self.change_version = 0 # Non-zero if we are in a change list
self.change_lines = [] # Lines of the current change
@@ -452,6 +454,8 @@
# Detect Change-Id tags
elif change_id_match:
+ if self.keep_change_id:
+ out = [line]
value = change_id_match.group(1)
if self.is_log:
if self.commit.change_id:
@@ -763,7 +767,7 @@
pst.finalise()
return series
-def fix_patch(backup_dir, fname, series, cmt):
+def fix_patch(backup_dir, fname, series, cmt, keep_change_id=False):
"""Fix up a patch file, by adding/removing as required.
We remove our tags from the patch file, insert changes lists, etc.
@@ -776,6 +780,7 @@
fname (str): Filename to patch file to process
series (Series): Series information about this patch set
cmt (Commit): Commit object for this patch file
+ keep_change_id (bool): Keep the Change-Id tag.
Return:
list: A list of errors, each str, or [] if all ok.
@@ -783,7 +788,7 @@
handle, tmpname = tempfile.mkstemp()
outfd = os.fdopen(handle, 'w', encoding='utf-8')
infd = open(fname, 'r', encoding='utf-8')
- pst = PatchStream(series)
+ pst = PatchStream(series, keep_change_id=keep_change_id)
pst.commit = cmt
pst.process_stream(infd, outfd)
infd.close()
@@ -795,7 +800,7 @@
shutil.move(tmpname, fname)
return cmt.warn
-def fix_patches(series, fnames):
+def fix_patches(series, fnames, keep_change_id=False):
"""Fix up a list of patches identified by filenames
The patch files are processed in place, and overwritten.
@@ -803,6 +808,7 @@
Args:
series (Series): The Series object
fnames (:type: list of str): List of patch files to process
+ keep_change_id (bool): Keep the Change-Id tag.
"""
# Current workflow creates patches, so we shouldn't need a backup
backup_dir = None #tempfile.mkdtemp('clean-patch')
@@ -811,7 +817,8 @@
cmt = series.commits[count]
cmt.patch = fname
cmt.count = count
- result = fix_patch(backup_dir, fname, series, cmt)
+ result = fix_patch(backup_dir, fname, series, cmt,
+ keep_change_id=keep_change_id)
if result:
print('%d warning%s for %s:' %
(len(result), 's' if len(result) > 1 else '', fname))
diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst
index 038b651..a8b317e 100644
--- a/tools/patman/patman.rst
+++ b/tools/patman/patman.rst
@@ -371,11 +371,12 @@
Separate each tag with a comma.
Change-Id:
- This tag is stripped out but is used to generate the Message-Id
- of the emails that will be sent. When you keep the Change-Id the
- same you are asserting that this is a slightly different version
- (but logically the same patch) as other patches that have been
- sent out with the same Change-Id.
+ This tag is used to generate the Message-Id of the emails that
+ will be sent. When you keep the Change-Id the same you are
+ asserting that this is a slightly different version (but logically
+ the same patch) as other patches that have been sent out with the
+ same Change-Id. The Change-Id tag line is removed from outgoing
+ patches, unless the `keep_change_id` settings is set to `True`.
Various other tags are silently removed, like these Chrome OS and
Gerrit tags::
diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py
index 0a8f740..db7860f 100644
--- a/tools/patman/test_checkpatch.py
+++ b/tools/patman/test_checkpatch.py
@@ -209,6 +209,22 @@
rc = os.system('diff -u %s %s' % (inname, expname))
self.assertEqual(rc, 0)
+ os.remove(inname)
+
+ # Test whether the keep_change_id settings works.
+ inhandle, inname = tempfile.mkstemp()
+ infd = os.fdopen(inhandle, 'w', encoding='utf-8')
+ infd.write(data)
+ infd.close()
+
+ patchstream.fix_patch(None, inname, series.Series(), com,
+ keep_change_id=True)
+
+ with open(inname, 'r') as f:
+ content = f.read()
+ self.assertIn(
+ 'Change-Id: I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413',
+ content)
os.remove(inname)
os.remove(expname)
diff --git a/tools/u_boot_pylib/command.py b/tools/u_boot_pylib/command.py
index 9bbfc5b..bbe95d8 100644
--- a/tools/u_boot_pylib/command.py
+++ b/tools/u_boot_pylib/command.py
@@ -105,9 +105,7 @@
last_pipe.communicate_filter(output_func))
if result.stdout and oneline:
result.output = result.stdout.rstrip(b'\r\n')
- result.return_code = last_pipe.wait()
- else:
- result.return_code = os.waitpid(last_pipe.pid, 0)[1]
+ result.return_code = last_pipe.wait()
if raise_on_error and result.return_code:
raise Exception("Error running '%s'" % user_pipestr)
return result.to_output(binary)