microblaze: Flush caches before enabling them
Flushing caches is necessary because of soft reset
which doesn't clear caches.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Reviewed-by: Marek Vasut <marex@denx.de>
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 8564c4e..3da711d 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -132,6 +132,12 @@
rsubi r8, r10, 0x26
sh r6, r0, r8
+ /* Flush cache before enable cache */
+ addik r5, r0, 0
+ addik r6, r0, XILINX_DCACHE_BYTE_SIZE
+flush: bralid r15, flush_cache
+ nop
+
/* enable instruction and data cache */
mfs r12, rmsr
ori r12, r12, 0xa0