pci: layerscape: Remove the shadow SVR definitions
This patch moves the SVR definitions to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 887954e..bd41df1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -16,6 +16,7 @@
#include <asm/arch/immap_lsch3.h>
#endif
#endif
+#include <asm/arch/svr.h>
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
#define gur_in32(a) in_le32(a)
@@ -77,38 +78,6 @@
#endif
#endif
#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1012A 0x870400
-#define SVR_LS1043A 0x879200
-#define SVR_LS1023A 0x879208
-/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
-#define SVR_LS1043A_P23 0x879202
-#define SVR_LS1023A_P23 0x87920A
-#define SVR_LS1017A 0x870B24
-#define SVR_LS1018A 0x870B20
-#define SVR_LS1027A 0x870B04
-#define SVR_LS1028A 0x870B00
-#define SVR_LS1046A 0x870700
-#define SVR_LS1026A 0x870708
-#define SVR_LS1048A 0x870320
-#define SVR_LS1084A 0x870302
-#define SVR_LS1088A 0x870300
-#define SVR_LS1044A 0x870322
-#define SVR_LS2045A 0x870120
-#define SVR_LS2080A 0x870110
-#define SVR_LS2085A 0x870100
-#define SVR_LS2040A 0x870130
-#define SVR_LS2088A 0x870900
-#define SVR_LS2084A 0x870910
-#define SVR_LS2048A 0x870920
-#define SVR_LS2044A 0x870930
-#define SVR_LS2081A 0x870918
-#define SVR_LS2041A 0x870914
-#define SVR_LX2160A 0x873600
-#define SVR_LX2120A 0x873620
-#define SVR_LX2080A 0x873602
-#define SVR_LX2162A 0x873608
-#define SVR_LX2122A 0x873628
-#define SVR_LX2082A 0x87360A
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/svr.h b/arch/arm/include/asm/arch-fsl-layerscape/svr.h
new file mode 100644
index 0000000..e37c4a8
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/svr.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_
+
+#define SVR_LS1012A 0x870400
+#define SVR_LS1043A 0x879200
+#define SVR_LS1023A 0x879208
+/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
+#define SVR_LS1043A_P23 0x879202
+#define SVR_LS1023A_P23 0x87920A
+#define SVR_LS1017A 0x870B24
+#define SVR_LS1018A 0x870B20
+#define SVR_LS1027A 0x870B04
+#define SVR_LS1028A 0x870B00
+#define SVR_LS1046A 0x870700
+#define SVR_LS1026A 0x870708
+#define SVR_LS1048A 0x870320
+#define SVR_LS1084A 0x870302
+#define SVR_LS1088A 0x870300
+#define SVR_LS1044A 0x870322
+#define SVR_LS2045A 0x870120
+#define SVR_LS2080A 0x870110
+#define SVR_LS2085A 0x870100
+#define SVR_LS2040A 0x870130
+#define SVR_LS2088A 0x870900
+#define SVR_LS2084A 0x870910
+#define SVR_LS2048A 0x870920
+#define SVR_LS2044A 0x870930
+#define SVR_LS2081A 0x870918
+#define SVR_LS2041A 0x870914
+#define SVR_LX2160A 0x873600
+#define SVR_LX2120A 0x873620
+#define SVR_LX2080A 0x873602
+#define SVR_LX2162A 0x873608
+#define SVR_LX2122A 0x873628
+#define SVR_LX2082A 0x87360A
+
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/svr.h b/arch/arm/include/asm/arch-ls102xa/svr.h
new file mode 100644
index 0000000..52b27e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/svr.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef _ASM_LS102X_SVR_H_
+#define _ASM_LS102X_SVR_H_
+
+#define SVR_LS102XA 0
+#define SVR_VAR_PER_SHIFT 8
+#define SVR_LS102XA_MASK 0x700
+
+#endif /* _ASM_LS102X_SVR_H_ */
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 0124e8e..8cdf516 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -10,6 +10,8 @@
#include <pci.h>
#include <linux/sizes.h>
+#include <asm/arch-fsl-layerscape/svr.h>
+#include <asm/arch-ls102xa/svr.h>
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
@@ -121,16 +123,6 @@
/* CS2 */
#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */
-#define SVR_LS102XA 0
-#define SVR_VAR_PER_SHIFT 8
-#define SVR_LS102XA_MASK 0x700
-#define SVR_LS2088A 0x870900
-#define SVR_LS2084A 0x870910
-#define SVR_LS2048A 0x870920
-#define SVR_LS2044A 0x870930
-#define SVR_LS2081A 0x870918
-#define SVR_LS2041A 0x870914
-
/* LS1021a PCIE space */
#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL