commit 5a4baa33e4d0beb9708719160bfc3f91a8f9f3bf
author Michal Simek <michal.simek@xilinx.com> Thu Dec 10 15:32:11 2015 +0100
committer Michal Simek <michal.simek@xilinx.com> Wed Jan 27 15:55:52 2016 +0100
tree 876fadcf9720a1a15c7990e599dc366f18bfeb65
parent 3af709092c6d92cf7e4e19a45fbb96e2e4d1c8f5

net: emaclite: Use indirect register access for TX reset

Move to use indirect register access when timeout expires for resetting
TX buffers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

drivers/net/xilinx_emaclite.c

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 724b61e..72b6e0a 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -408,6 +408,7 @@
 	u32 reg;
 	u32 baseaddress;
 	struct xemaclite *emaclite = dev->priv;
+	struct emaclite_regs *regs = emaclite->regs;
 
 	u32 maxtry = 1000;
 
@@ -422,10 +423,9 @@
 	if (!maxtry) {
 		printf("Error: Timeout waiting for ethernet TX buffer\n");
 		/* Restart PING TX */
-		out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
+		out_be32(&regs->tx_ping_tsr, 0);
 		if (emaclite->txpp) {
-			out_be32 (dev->iobase + XEL_TSR_OFFSET +
-				XEL_BUFFER_OFFSET, 0);
+			out_be32(&regs->tx_pong_tsr, 0);
 		}
 		return -1;
 	}