commit 5b7672fc49af1b771a7e318522b010fd5b11c4ab
author Prabhakar Kushwaha <prabhakar@freescale.com> Mon Jan 27 15:55:20 2014 +0530
committer York Sun <yorksun@freescale.com> Mon Feb 03 08:38:48 2014 -0800
tree 861555e4cd4460716f865eadee507cbc87738d65
parent 96bda02c9e3a209a1e972a337937c9c43fc538f6

boards/t1040qds: Adds ethernet support for T1040

Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
    Define MDIO related configs
    Added eth.c file
    Update t1040.c to support RGMII and SGMII
    Update t1040qds.c to support ethernet
    Define the PHY address

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

drivers/net/fm/t1040.c

diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
index 83cf081..bcc871d 100644
--- a/drivers/net/fm/t1040.c
+++ b/drivers/net/fm/t1040.c
@@ -12,5 +12,61 @@
 
 phy_interface_t fman_port_enet_if(enum fm_port port)
 {
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+	/* handle RGMII first */
+	if ((port == FM1_DTSEC2) &&
+	    ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
+			FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
+		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
+			return PHY_INTERFACE_MODE_RGMII;
+		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
+			return PHY_INTERFACE_MODE_MII;
+		else
+			return PHY_INTERFACE_MODE_NONE;
+	}
+
+	if ((port == FM1_DTSEC4) &&
+	    ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
+			FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
+		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
+			return PHY_INTERFACE_MODE_RGMII;
+		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+				FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
+			return PHY_INTERFACE_MODE_MII;
+		else
+			return PHY_INTERFACE_MODE_NONE;
+	}
+
+	if (port == FM1_DTSEC5) {
+		if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+				FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
+			return PHY_INTERFACE_MODE_RGMII;
+		else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+				FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
+			return PHY_INTERFACE_MODE_MII;
+		else
+			return PHY_INTERFACE_MODE_NONE;
+	}
+
+	switch (port) {
+	case FM1_DTSEC1:
+	case FM1_DTSEC2:
+		if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1))
+			return PHY_INTERFACE_MODE_QSGMII;
+	case FM1_DTSEC3:
+	case FM1_DTSEC4:
+	case FM1_DTSEC5:
+		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+			return PHY_INTERFACE_MODE_SGMII;
+		break;
+	default:
+		return PHY_INTERFACE_MODE_NONE;
+	}
+
 	return PHY_INTERFACE_MODE_NONE;
 }