commit 5c16c54124ba7a21979e1eb656e696b7b6d881ec
author Amit Virdi <amit.virdi@st.com> Mon May 07 13:00:20 2012 +0530
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Sat Jul 07 14:07:38 2012 +0200
tree 480799414f62c779620bb0583e69cc52073d6957
parent f3fcf92d595b297b47a1b58b8ec39f93f40ef912

st_smi: Return error in case TFF is not set

Curently the code makes wrong assumption that the Transfer finished flag shall
be set within the stipulated time. However, there may occur a scenario in which
the TFF flag is not set. Return error in that case.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>

drivers/mtd/st_smi.c

diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index db08ab9..9769b28 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@ -58,13 +58,15 @@
  *
  * Wait until TFF is set in status register
  */
-static void smi_wait_xfer_finish(int timeout)
+static int smi_wait_xfer_finish(int timeout)
 {
-	while (timeout--) {
+	do {
 		if (readl(&smicntl->smi_sr) & TFF)
-			break;
+			return 0;
 		udelay(1000);
-	}
+	} while (timeout--);
+
+	return -1;
 }
 
 /*
@@ -83,7 +85,8 @@
 	writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
 	       &smicntl->smi_cr2);
 
-	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+	if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
+		return -EIO;
 
 	value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
 
@@ -151,7 +154,8 @@
 	/* Performing a RSR instruction in HW mode */
 	writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
 
-	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+	if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
+		return -1;
 
 	/* Restore the CTRL REG1 state */
 	writel(ctrlreg1, &smicntl->smi_cr1);
@@ -211,7 +215,8 @@
 	/* Give the Flash, Write Enable command */
 	writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
 
-	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+	if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
+		return -1;
 
 	/* Restore the CTRL REG1 state */
 	writel(ctrlreg1, &smicntl->smi_cr1);
@@ -292,7 +297,8 @@
 		writel(instruction, &smicntl->smi_tr);
 		writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
 		       &smicntl->smi_cr2);
-		smi_wait_xfer_finish(XFER_FINISH_TOUT);
+		if (smi_wait_xfer_finish(XFER_FINISH_TOUT))
+			return -EIO;
 
 		if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
 			return -EBUSY;