ppc4xx: Rework 440GX UIC handling
This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.
Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 01712b0..8a38335 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -169,12 +169,15 @@
* UIC. Only exception is 440GX where the EMAC interrupts are
* spread over two UIC's!
*/
+#if defined(CONFIG_440GX)
+#define UIC_BASE_MAL UIC1_DCR_BASE
+#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
+#define UIC_BASE_EMAC UIC2_DCR_BASE
+#define UIC_BASE_EMAC_B UIC3_DCR_BASE
+#else
#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
-#if defined(CONFIG_440GX)
-#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(2)) * 0x10))
-#else
#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
#endif